JESD251C：xSPI标准详解：非易失性存储器接口升级版

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JESD251C标准，全称为"EXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, Version 1.0"，是由JEDEC（固态技术协会）发布的一份重要规范。这个标准是JESD251B的修订版，于2021年9月更新，旨在为非易失性存储器设备提供一种扩展的串行外围接口（xSPI），以支持更高效、兼容和标准化的数据传输。 JESD251C关注的重点在于如何改进和扩展SPI（Serial Peripheral Interface）接口，这是一种广泛应用于嵌入式系统和消费电子中的通信协议，特别是在NVM（Non-Volatile Memory）如闪存、EEPROM等设备间进行数据交换。通过引入xSPI，该标准旨在解决传统SPI在高数据速率、多通道操作以及多设备连接方面的局限性，从而推动了整个行业的技术创新和发展。该标准的主要特点包括： 1. **高性能接口**：xSPI设计目的是支持更高的数据传输速度，以满足现代电子产品对快速数据读写的需求，尤其是在物联网(IoT)和移动设备领域，对存储性能有着极高的要求。 2. **多通道支持**：xSPI允许同时处理多个数据通道，提高了并行传输能力，这对于需要同时与多个NVM设备交互的系统至关重要。 3. **电气兼容性**：通过定义统一的信号规范，JESD251C确保不同供应商生产的设备之间能够无缝协作，减少了系统集成时的复杂性和潜在冲突。 4. **电源管理优化**：标准考虑到了功耗和电源管理，有助于设计出更加节能且易于集成的系统架构。 5. **文档透明度**：JEDEC作为制定者，确保了标准的公开性和可信赖性，所有内容都经过董事会和法律团队的审查，以保护制造商和消费者的权益。 6. **专利中立**：尽管标准可能涉及专利技术，但JEDEC的采用并不意味着对其专利的承认或承诺，而是为了公共利益和行业进步，鼓励创新和市场竞争。对于那些使用或设计包含xSPI接口的系统设计师、硬件工程师和半导体制造商来说，理解并遵循JESD251C标准至关重要，因为它不仅有助于提高产品的互换性和质量，还能加快产品上市时间，减少不必要的研发成本。随着技术的发展，JESD251C可能会持续演进，以适应未来NVM设备和系统的新需求。

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JEDEC Standard No. 251C

Page 4

3.1 Acronyms

DDR

Double Data Rate. Data is transferred on each edge of a related clock.

Gigabyte: 1,073,741,824 or 2

bytes.

I/O or IO

Input or Output – A signal port that may receive or drive voltage levels to communicate

with other devices.

Kilobyte: 1024 or 2

bytes.

Megabyte: 1,048,576 or 2

bytes

MB/s

Megabytes per second

MSb, LSb

Most Significant Bit or Least Significant Bit

MT/s

Mega Transfers per second

NVM

Non-Volatile Memory

Unit Interval; It is one bit nominal time. For example, UI=5 ns at 200 MHz SDR, UI =

2.5 ns for 200 MHz DDR.

xSPI

eXtended Serial Peripheral Interface

3.2 Conventions

This standard follows some conventions used in other JEDEC documents.

A binary number is represented in this standard by any sequence of digits consisting of only the Western-

Arabic numerals 0 and 1 immediately followed by a lower-case b (e.g., 0101b). Spaces may be included

in binary number representations to increase readability or delineate field boundaries (e.g., 0 0101 1010b).

A hexadecimal number is represented in this standard by any sequence of digits consisting of only the

Western-Arabic numerals 0 through 9 and/or the upper-case English letters A through F

immediately followed by a lower-case h (e.g., FA23h). Spaces may be included in hexadecimal number

representations to increase readability or delineate field boundaries (e.g., B FD8C FA23h).

A decimal number is represented in this standard by any sequence of digits consisting of only

the Western-Arabic numerals 0 through 9 not immediately followed by a lower-case b or lower-case h

(e.g., 25).

A range of numeric values is represented in this standard in the form "a to z", where a is the first value

included in the range, all values between a and z are included in the range, and z is the last value included

in the range (e.g., the representation "0h to 3h" includes the values 0h, 1h, 2h, and 3h).

Other conventions used in this document:

Signals that are considered active when LOW have signal names that end with the hash / pound special

character (i.e., have a suffix of #).

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JEDEC Standard No. 251C

Page 5

3.3 Keywords

Several keywords are used to differentiate levels of requirements and options, as follow:

Can - A keyword used for statements of possibility and capability, whether material, physical, or causal

(can equals is able to).

Expected - A keyword used to describe the behavior of the hardware or software in the design models

assumed by this standard. Other hardware and software design models may also be implemented.

Ignored - A keyword that describes bits, bytes, or fields whose values are not checked by the recipient.

Mandatory - A keyword that indicates items required to be implemented as defined by this standard.

May - A keyword that indicates a course of action permissible within the limits of the standard

(may equals is permitted).

Must - The use of the word must is deprecated and shall not be used when stating mandatory

requirements; must is used only to describe unavoidable situations.

Obsolete - A keyword indicating that an item was defined in prior standards but has been removed from

this standard.

Optional - A keyword that describes features which are not required to be implemented by this standard.

However, if any optional feature defined by the standard is implemented, it shall be implemented

as defined by the standard.

Preferred – A keyword used to identify a feature option which is the preferred option to implement for

compliance with anticipated future revisions of this standard.

Reserved - A keyword used to describe objects—bits, bytes, and fields—or the code values assigned to

these objects in cases where either the object or the code value is set aside for future

standardization.

Usage and interpretation may be specified by future extensions to this or other standards. A

reserved object shall be zeroed or, upon development of a future standard, set to a value

specified by such a standard. The recipient of a reserved object shall not check its value. The recipient

of a defined object shall check its value and reject reserved code values.

Shall - A keyword that indicates a mandatory requirement strictly to be followed in order to conform to

the standard and from which no deviation is permitted (“shall” equals “is required to”). Designers are

required to implement all such mandatory requirements to assure interoperability with other products

conforming to this standard.

Should - A keyword used to indicate that among several possibilities one is recommended as particularly

suitable, without mentioning or excluding others; or that a certain course of action is preferred but not

necessarily required; or that (in the negative form) a certain course of action is deprecated but

not prohibited (“should” equals “is recommended that”).

Will - The use of the word will is deprecated and shall not be used when stating mandatory requirements;

will is only used in statements of fact.

3.4 Abbreviations

etc.: And so forth (Latin: et cetera)

e.g.: For example (Latin: exempli gratia)

i.e.: That is (Latin: id est)

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JEDEC Standard No. 251C

Page 7

5 xSPI Overview

5.1 xSPI Performance Enhancements

Serial interface performance can be enhanced by increasing the basic clock rate, adding source

synchronous clocking, using Double Data Rate (DDR), or by adding parallel data (IO) lines. xSPI allows

all four methods.

Higher clock rates with accurate information transfer are possible by using a separate clock signal for

each direction of information transfer. This is known as source synchronous clocking; providing a timing

reference (clock / strobe) from the source of information, with minimum skew relative to the related

information (data). This enables accurate timing of information capture at the destination device as the

period of valid information decreases at higher clock rates.

DDR can be used to double performance by relating information transfers to both rising and falling edges

of the timing reference.

Up to 8 parallel data (IO) lines are used in xSPI to further increase system performance by transferring

more parallel bits in each clock cycle.

5.2 xSPI Topology and Signal Descriptions

xSPI has a single controller, multiple target bus topology with source synchronous clocking.

Each target device is selected by a separate LOW active Chip Select (CS#) signal from the controller

device.

A clock (CK) signal from the controller to all target devices provides a timing reference for interface

operations. The clock is the timing reference for information transfer on the IO signals from the

controller to the selected target. The clock is also a timing reference for interface operations within the

controller and target interface logic, such as the counting of access latency time. The clock may optionally

be provided by the controller as a differential clock using two signals (CK and CK#). The remaining text

and block diagrams in this standard may only describe one clock (CK) signal for simplicity but, where

ever CK is described or illustrated, a differential pair of CK, CK# may be used. Some xSPI compliant

target devices require a differential clock. A differential clock reduces clock duty cycle distortion and

effectively doubles the clock slew rate, providing improved timing margins for target devices using a

differential clock.

The IO signals provide a bidirectional, variable width path, for information transfer between the controller

and selected target. Different targets on the same bus may use a different IO width for information

transfer.

The Data Strobe (DS) signal provides a timing reference for information transfer on the IO signals from

the target to the controller. DS is an output signal from the xSPI target device that is aligned with the

edges of output data and is used by the controller interface to optimize high frequency read data capture.

DS may optionally be used as a signal from the target to the controller, to indicate the duration of initial

access latency or, as a signal from the controller to the target, to indicate write data masking.

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