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首页GD32F4xx 用户手册:基于 Cortex-M4 的 32 位 MCU
GD32F4xx 用户手册:基于 Cortex-M4 的 32 位 MCU
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更新于2024-07-09
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"GD32F4xx 用户手册 Rev2.4.pdf"
本文档是 GigaDevice Semiconductor Inc. 为 GD32F405xx、GD32F407xx 和 GD32F450xx 系列微控制器(MCU)编写的用户手册,基于 Arm Cortex-M4 32 位架构。手册详细介绍了这些微控制器的系统和内存架构,以及相关功能。
1. Arm Cortex-M4 处理器:
Arm Cortex-M4 是一种高性能、低功耗的处理器内核,具有浮点单元(FPU),适用于实时应用和嵌入式计算。它支持Thumb-2指令集,提供高效代码执行。
2. 系统架构:
GD32F4xx 的系统架构包括各种外设接口、时钟和电源管理系统,以及中断和调试模块。该架构设计旨在优化性能、灵活性和能源效率。
3. 内存映射:
- Bit-banding: 允许直接对每个内存地址的位进行访问和修改,提高编程效率。
- On-chip SRAM: 集成在芯片内部的静态随机访问存储器,用于快速数据交换。
- On-chip Flash Memory: 存储程序代码和配置数据,分为不同的区块,支持在线编程和安全擦写。
4. 引脚配置:
GD32F4xx 提供多种外部中断(EXTI)源选择,通过 SYSCFG 寄存器进行配置,如 SYSCFG_EXTISS0 至 SYSCFG_EXTISS3,用于灵活地连接外部设备事件到处理器中断线。
5. I/O 补偿控制:
SYSCFG_CPSCTL 寄存器用于管理输入/输出端口的补偿,确保高速信号在不同负载条件下的稳定性。
6. 设备电子签名:
包含内存密度信息,用于识别芯片的存储容量;以及唯一的 96 位设备 ID,用于设备认证和防伪。
7. Flash 内存控制器 (FMC):
FMC 负责管理和控制片上 Flash 存储器的读写操作,支持快速访问、预取功能和错误检测与校正机制。此外,还提供了闪存编程和擦除的时间表以及保护机制。
8. 外设接口:
手册还涵盖了 GD32F4xx 中的其他外设,如定时器、串行通信接口(SPI/I2C/UART)、CAN 总线、USB 接口、以太网控制器、ADC、DAC、DMA、CRC 计算单元等。这些外设丰富了微控制器的应用场景,可用于工业控制、物联网、音频处理等多种领域。
9. 系统配置寄存器 (SYSCFG):
SYSCFG 提供了对系统配置的控制,例如配置外部中断源、电压检测阈值、电机控制PWM配置等,以满足不同应用的需求。
10. 开发工具和软件支持:
用户手册通常会提及开发环境、IDE、调试器以及GigaDevice提供的固件库,帮助开发者快速进行应用程序开发和系统集成。
GD32F4xx 系列MCU是针对高性能应用而设计的,具备强大的处理能力、丰富的外设接口和灵活的系统配置选项。用户手册详细阐述了其功能和使用方法,为开发者提供了全面的技术指南。
![](https://csdnimg.cn/release/download_crawler_static/39637073/bg10.jpg)
GD32F4xx User Manual
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23.5.6. Dithering function ............................................................................................................................ 653
23.6. Interrupts ..................................................................................................................... 653
23.7. Register definition ........................................................................................................ 654
23.7.1. Synchronous pulse size register (TLI_SPSZ) ............................................................................ 654
23.7.2. Back-porch size register (TLI_BPSZ) .......................................................................................... 654
23.7.3. Active size register (TLI_ASZ) ...................................................................................................... 655
23.7.4. Total size register (TLI_TSZ) ......................................................................................................... 655
23.7.5. Control register (TLI_CTL) ............................................................................................................ 656
23.7.6. Reload layer register (TLI_RL) ..................................................................................................... 657
23.7.7. Background color register (TLI_BGC) ......................................................................................... 658
23.7.8. Interrupt enable register (TLI_INTEN) ......................................................................................... 658
23.7.9. Interrupt flag register (TLI_INTF) .................................................................................................. 659
23.7.10. Interrupt flag clear register (TLI_INTC) ................................................................................... 660
23.7.11. Line mark register (TLI_LM) ...................................................................................................... 660
23.7.12. Current pixel position register (TLI_CPPOS) ......................................................................... 661
23.7.13. Status register (TLI_STAT) ........................................................................................................ 661
23.7.14. Layer x control register (TLI_LxCTL) ....................................................................................... 662
23.7.15. Layer x horizontal position parameters register (TLI_LxHPOS) .......................................... 662
23.7.16. Layer x vertical position parameters register (TLI_LxVPOS) ............................................... 663
23.7.17. Layer x color key register (TLI_LxCKEY) ................................................................................ 663
23.7.18. Layer x packeted pixel format register (TLI_LxPPF) ............................................................. 664
23.7.19. Layer x specified alpha register (TLI_LxSA) .......................................................................... 665
23.7.20. Layer x default color register (TLI_LxDC) ............................................................................... 665
23.7.21. Layer x blending register (TLI_LxBLEND) .............................................................................. 666
23.7.22. Layer x frame base address register (TLI_LxFBADDR) ....................................................... 666
23.7.23. Layer x frame line length register (TLI_LxFLLEN)................................................................. 667
23.7.24. Layer x frame total line number register (TLI_LxFTLN) ........................................................ 667
23.7.25. Layer x look up table register (TLI_LxLUT) ............................................................................ 668
24. Secure digital input/output interface (SDIO) ..................................................... 669
24.1. Introduction ................................................................................................................. 669
24.2. Main features ............................................................................................................... 669
24.3. SDIO bus topology ........................................................................................................ 669
24.4. SDIO functional description........................................................................................... 672
24.4.1. SDIO adapter .................................................................................................................................. 672
24.4.2. APB2 interface ................................................................................................................................ 676
24.5. Card functional description ........................................................................................... 678
24.5.1. Card registers .................................................................................................................................. 678
24.5.2. Commands ...................................................................................................................................... 679
24.5.3. Responses ....................................................................................................................................... 691
24.5.4. Data packets format ....................................................................................................................... 696
24.5.5. Two status fields of the card .......................................................................................................... 697
![](https://csdnimg.cn/release/download_crawler_static/39637073/bg11.jpg)
GD32F4xx User Manual
17
24.6. Programming sequence ................................................................................................ 704
24.6.1. Card identification ........................................................................................................................... 704
24.6.2. No data commands ........................................................................................................................ 706
24.6.3. Single block or multiple block write .............................................................................................. 706
24.6.4. Single block or multiple block read ............................................................................................... 708
24.6.5. Stream write and stream read (MMC only) ................................................................................. 709
24.6.6. Erase ................................................................................................................................................ 710
24.6.7. Bus width selection ......................................................................................................................... 711
24.6.8. Protection management ................................................................................................................. 711
24.6.9. Card Lock/Unlock operation .......................................................................................................... 712
24.7. Specific operations ....................................................................................................... 714
24.7.1. SD I/O specific operations ............................................................................................................. 714
24.7.2. CE-ATA specific operations ........................................................................................................... 718
24.8. SDIO registers ............................................................................................................... 720
24.8.1. Power control register (SDIO_PWRCTL) .................................................................................... 720
24.8.2. Clock control register (SDIO_CLKCTL) ....................................................................................... 720
24.8.3. Command argument register (SDIO_CMDAGMT) .................................................................... 722
24.8.4. Command control register (SDIO_CMDCTL) ............................................................................. 722
24.8.5. Command index response register (SDIO_RSPCMDIDX) ....................................................... 724
24.8.6. Response register (SDIO_RESPx x=0..3) .................................................................................. 724
24.8.7. Data timeout register (SDIO_DATATO) ....................................................................................... 725
24.8.8. Data length register (SDIO_DATALEN) ....................................................................................... 725
24.8.9. Data control register (SDIO_DATACTL) ...................................................................................... 726
24.8.10. Data counter register (SDIO_DATACNT) ................................................................................ 727
24.8.11. Status register (SDIO_STAT) .................................................................................................... 728
24.8.12. Interrupt clear register (SDIO_INTC) ....................................................................................... 729
24.8.13. Interrupt enable register (SDIO_INTEN) ................................................................................. 731
24.8.14. FIFO counter register (SDIO_FIFOCNT) ................................................................................ 732
24.8.15. FIFO data register (SDIO_FIFO) .............................................................................................. 733
25. External memory controller (EXMC) .................................................................. 734
25.1. Overview ...................................................................................................................... 734
25.2. Characteristics .............................................................................................................. 734
25.3. Function overview ........................................................................................................ 734
25.3.1. Block diagram .................................................................................................................................. 734
25.3.2. Basic regulation of EXMC access ................................................................................................ 735
25.3.3. External device address mapping ................................................................................................ 736
25.3.4. NOR/PSRAM controller ................................................................................................................. 740
25.3.5. NAND flash or PC card controller ................................................................................................. 762
25.3.6. SDRAM controller ........................................................................................................................... 767
25.4. Register definition ........................................................................................................ 779
25.4.1. NOR/PSRAM controller registers ................................................................................................. 779
![](https://csdnimg.cn/release/download_crawler_static/39637073/bg12.jpg)
GD32F4xx User Manual
18
25.4.2. NAND flash/PC card controller registers ..................................................................................... 784
25.4.3. SDRAM controller registers ........................................................................................................... 790
25.4.4. SQPI-PSRAM controller registers ................................................................................................ 797
26. Controller area network (CAN) ........................................................................... 801
26.1. Overview ...................................................................................................................... 801
26.2. Characteristics .............................................................................................................. 801
26.3. Function overview ........................................................................................................ 802
26.3.1. Working mode ................................................................................................................................. 802
26.3.2. Communication modes .................................................................................................................. 803
26.3.3. Data transmission ........................................................................................................................... 804
26.3.4. Data reception ................................................................................................................................. 806
26.3.5. Filtering function .............................................................................................................................. 808
26.3.6. Time-triggered communication ..................................................................................................... 811
26.3.7. Communication parameters .......................................................................................................... 811
26.3.8. Error flags ........................................................................................................................................ 813
26.3.9. CAN interrupts ................................................................................................................................. 814
26.4. CAN registers ................................................................................................................ 816
26.4.1. Control register (CAN_CTL) .......................................................................................................... 816
26.4.2. Status register (CAN_STAT) ......................................................................................................... 817
26.4.3. Transmit status register (CAN_TSTAT) ....................................................................................... 819
26.4.4. Receive message FIFO0 register (CAN_RFIFO0) .................................................................... 822
26.4.5. Receive message FIFO1 register (CAN_RFIFO1) .................................................................... 822
26.4.6. Interrupt enable register (CAN_INTEN) ...................................................................................... 823
26.4.7. Error register (CAN_ERR) ............................................................................................................. 825
26.4.8. Bit timing register (CAN_BT) ......................................................................................................... 826
26.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ........................................................ 827
26.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2) ................................................... 827
26.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2) .............................................. 828
26.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) .............................................. 829
26.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) ................................... 829
26.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) .................................. 830
26.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) ............................. 830
26.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) ............................. 831
26.4.17. Filter control register (CAN_FCTL) .......................................................................................... 831
26.4.18. Filter mode configuration register (CAN_FMCFG) ................................................................ 832
26.4.19. Filter scale configuration register (CAN_FSCFG) ................................................................. 833
26.4.20. Filter associated FIFO register (CAN_FAFIFO) ..................................................................... 833
26.4.21. Filter working register (CAN_FW) ............................................................................................ 834
26.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) ..................................................... 834
27. Ethernet (ENET) .................................................................................................... 836
27.1. Overview ...................................................................................................................... 836
![](https://csdnimg.cn/release/download_crawler_static/39637073/bg13.jpg)
GD32F4xx User Manual
19
27.2. Characteristics .............................................................................................................. 836
27.2.1. Block diagram .................................................................................................................................. 837
27.2.2. MAC 802.3 Ethernet packet description ...................................................................................... 838
27.2.3. Ethernet signal description ............................................................................................................ 839
27.3. Function overview ........................................................................................................ 840
27.3.1. Interface configuration ................................................................................................................... 840
27.3.2. MAC function overview .................................................................................................................. 844
27.3.3. MAC statistics counters: MSC ...................................................................................................... 856
27.3.4. Wake up management: WUM ....................................................................................................... 856
27.3.5. Precision time protocol: PTP ......................................................................................................... 860
27.3.6. DMA controller description ............................................................................................................ 864
27.3.7. Example for a typical configuration flow of Ethernet ................................................................. 888
27.3.8. Ethernet interrupts .......................................................................................................................... 890
27.4. Register definition ........................................................................................................ 892
27.4.1. MAC configuration register (ENET_MAC_CFG) ........................................................................ 892
27.4.2. MAC frame filter register (ENET_MAC_FRMF) ......................................................................... 894
27.4.3. MAC hash list high register (ENET_MAC_HLH) ........................................................................ 896
27.4.4. MAC hash list low register (ENET_MAC_HLL) .......................................................................... 896
27.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) ................................................................ 897
27.4.6. MAC MII data register (ENET_MAC_PHY_DATA) .................................................................... 898
27.4.7. MAC flow control register (ENET_MAC_FCTL) ......................................................................... 898
27.4.8. MAC VLAN tag register (ENET_MAC_VLT) ............................................................................... 900
27.4.9. MAC remote wakeup frame filter register (ENET_MAC_RWFF) ............................................. 900
27.4.10. MAC wakeup management register (ENET_MAC_WUM) ................................................... 901
27.4.11. MAC debug register (ENET_MAC_DBG) ............................................................................... 902
27.4.12. MAC interrupt flag register (ENET_MAC_INTF) .................................................................... 904
27.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) ........................................................... 905
27.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) ........................................................ 905
27.4.15. MAC address 0 low register (ENET_MAC_ADDR0L) ........................................................... 906
27.4.16. MAC address 1 high register (ENET_MAC_ADDR1H) ........................................................ 906
27.4.17. MAC address 1 low register (ENET_MAC_ADDR1L) ........................................................... 907
27.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) ........................................................ 907
27.4.19. MAC address 2 low register (ENET_MAC_ADDR2L) ........................................................... 908
27.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) ........................................................ 909
27.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) ........................................................... 909
27.4.22. MAC flow control threshold register (ENET_MAC_FCTH) ................................................... 910
27.4.23. MSC control register (ENET_MSC_CTL) ............................................................................... 911
27.4.24. MSC receive interrupt flag register (ENET_MSC_RINTF) ................................................... 912
27.4.25. MSC transmit interrupt flag register (ENET_MSC_TINTF) .................................................. 912
27.4.26. MSC receive interrupt mask register (ENET_MSC_RINTMSK) .......................................... 913
27.4.27. MSC transmit interrupt mask register (ENET_MSC_TINTMSK) ......................................... 914
27.4.28. MSC transmitted good frames after a single collision counter register
(ENET_MSC_SCCNT) ................................................................................................................................... 915
![](https://csdnimg.cn/release/download_crawler_static/39637073/bg14.jpg)
GD32F4xx User Manual
20
27.4.29. MSC transmitted good frames after more than a single collision counter register
(ENET_MSC_MSCCNT) ................................................................................................................................ 915
27.4.30. MSC transmitted good frames counter register (ENET_MSC_TGFCNT).......................... 916
27.4.31. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT) .......... 916
27.4.32. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT) .. 916
27.4.33. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT) ............. 917
27.4.34. PTP time stamp control register (ENET_PTP_TSCTL) ........................................................ 917
27.4.35. PTP subsecond increment register (ENET_PTP_SSINC) ................................................... 920
27.4.36. PTP time stamp high register (ENET_PTP_TSH) ................................................................. 920
27.4.37. PTP time stamp low register (ENET_PTP_TSL) ................................................................... 921
27.4.38. PTP time stamp update high register (ENET_PTP_TSUH) ................................................. 921
27.4.39. PTP time stamp update low register (ENET_PTP_TSUL) ................................................... 922
27.4.40. PTP time stamp addend register (ENET_PTP_TSADDEND) ............................................. 922
27.4.41. PTP expected time high register (ENET_PTP_ETH) ............................................................ 923
27.4.42. PTP expected time low register (ENET_PTP_ETL) .............................................................. 923
27.4.43. PTP time stamp flag register (ENET_PTP_TSF) ................................................................... 923
27.4.44. PTP PPS control register (ENET_PTP_PPSCTL) ................................................................. 924
27.4.45. DMA bus control register (ENET_DMA_BCTL) ..................................................................... 924
27.4.46. DMA transmit poll enable register (ENET_DMA_TPEN) ...................................................... 927
27.4.47. DMA receive poll enable register (ENET_DMA_RPEN) ....................................................... 927
27.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR) ........................ 928
27.4.49. DMA transmit descriptor table address register (ENET_DMA_TDTADDR) ....................... 928
27.4.50. DMA status register (ENET_DMA_STAT) ............................................................................... 929
27.4.51. DMA control register (ENET_DMA_CTL) ................................................................................ 932
27.4.52. DMA interrupt enable register (ENET_DMA_INTEN) ........................................................... 935
27.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT) ...... 937
27.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC) ............................. 937
27.4.55. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) ............................. 938
27.4.56. DMA current receive descriptor address register (ENET_DMA_CRDADDR) ........................ 938
27.4.57. DMA current transmit buffer address register (ENET_DMA_CTBADDR) .......................... 939
27.4.58. DMA current receive buffer address register (ENET_DMA_CRBADDR) ........................... 939
28. Universal serial bus full-speed interface (USBFS) .......................................... 940
28.1. Overview ...................................................................................................................... 940
28.2. Characteristics .............................................................................................................. 940
28.3. Block diagram ............................................................................................................... 941
28.4. Signal description ......................................................................................................... 941
28.5. Function overview ........................................................................................................ 941
28.5.1. USBFS clocks and working modes .............................................................................................. 941
28.5.2. USB host function ........................................................................................................................... 943
28.5.3. USB device function ....................................................................................................................... 945
28.5.4. OTG function overview .................................................................................................................. 946
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