EZ-USB FX3 技术参考手册：Cypress Semiconductor

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"EZ-USB FX3技术参考手册" EZ-USB FX3技术参考手册是一部针对Cypress Semiconductor公司的EZ-USB FX3系列微控制器的详细技术文档。该手册提供了丰富的信息，帮助开发者理解和应用这款高性能、低功耗的USB设备控制器。EZ-USB FX3结合了通用可编程逻辑（GPL）和USB 2.0接口，为设计人员提供了一个灵活的平台，用于创建定制化的USB外围设备解决方案。手册中的内容可能包括以下几个关键知识点： 1. **EZ-USB架构**：阐述了EZ-USB FX3的核心结构，包括其内嵌的ARM9处理器、可编程逻辑单元、内部存储器以及与外部设备的接口。 2. **USB协议支持**：详述了如何利用EZ-USB FX3实现USB 2.0全速和高速通信，包括设备枚举、数据传输、中断传输和批量传输等USB协议细节。 3. **通用可编程逻辑（GPL）**：介绍如何利用FX3中的GPL资源，定制硬件功能，如信号处理、协议转换或数据转换，以满足特定应用需求。 4. **软件开发**：涵盖了与FX3相关的固件和驱动程序开发，包括Cypress提供的CyAPI，这是一套高级API，简化了固件开发，并允许用户通过C或C++进行编程。 5. **硬件设计**：提供了GPIO（通用输入/输出）配置、电源管理、时钟和复用引脚的详细信息，帮助设计人员正确连接和配置FX3芯片。 6. **示例代码和应用实例**：手册可能包含演示如何使用EZ-USB FX3的各种示例代码，以及在不同应用领域的实际案例，如图像采集、数据记录和高速数据传输等。 7. **故障排查和调试**：提供了故障排查指南，帮助开发者识别并解决在开发和测试过程中遇到的问题。 8. **版权和许可信息**：强调了Cypress Semiconductor对文档和相关软件的所有权，并提醒用户在没有具体许可协议的情况下，不应擅自使用或修改附带的软件。通过这个技术参考手册，开发者可以全面了解EZ-USB FX3的各个方面，从而能够充分利用其性能，开发出符合USB标准且具有独特功能的创新产品。Cypress Semiconductor作为业界知名的半导体供应商，其提供的文档通常具有高度的专业性和完整性，是开发者的重要参考资料。

16 EZ-USB FX3 Technical Reference Manual., Spec No.: 001-76074 Rev. *D

Contents

10.18.5 I2S_EGRESS_DATA_LEFT ................................................................................ 544

10.18.6 I2S_EGRESS_DATA_RIGHT ..............................................................................545

10.18.7 I2S_COUNTER ....................................................................................................546

10.18.8 I2S_SOCKET .......................................................................................................547

10.18.9 I2S_ID ..................................................................................................................548

10.18.10 I2S_POWER ........................................................................................................549

10.19 I2C Registers........................................................................................................................550

10.19.1 I2C_CONFIG ....................................................................................................... 550

10.19.2 I2C_STATUS .......................................................................................................552

10.19.3 I2C_INTR .............................................................................................................554

10.19.4 I2C_INTR_MASK ................................................................................................. 555

10.19.5 I2C_TIMEOUT .....................................................................................................556

10.19.6 I2C_DMA_TIMEOUT ...........................................................................................557

10.19.7 I2C_PREAMBLE_CTRL ......................................................................................558

10.19.8 I2C_PREAMBLE_DATA ......................................................................................559

10.19.9 I2C_PREAMBLE_RPT .........................................................................................561

10.19.10 I2C_COMMAND ..................................................................................................562

10.19.11 I2C_EGRESS_DATA ........................................................................................... 564

10.19.12 I2C_INGRESS_DATA ..........................................................................................565

10.19.13 I2C_CLOCK_LOW_COUNT ................................................................................566

10.19.14 I2C_BYTE_COUNT .............................................................................................567

10.19.15 I2C_BYTES_TRANSFERRED .............................................................................568

10.19.16 I2C_SOCKET .......................................................................................................569

10.19.17 I2C_ID ..................................................................................................................570

10.19.18 I2C_POWER ........................................................................................................571

10.20 UART Registers.................................................................................................................... 572

10.20.1 UART_CONFIG ................................................................................................... 572

10.20.2 UART_STATUS ...................................................................................................574

10.20.3 UART_INTR .........................................................................................................576

10.20.4 UART_INTR_MASK .............................................................................................577

10.20.5 UART_EGRESS_DATA .......................................................................................578

10.20.6 UART_INGRESS_DATA .....................................................................................579

10.20.7 UART_SOCKET ..................................................................................................580

10.20.8 UART_RX_BYTE_COUNT ..................................................................................581

10.20.9 UART_TX_BYTE_COUNT ..................................................................................582

10.20.10 UART_ID ..............................................................................................................583

10.20.11 UART_POWER ....................................................................................................584

10.21 SPI Registers........................................................................................................................585

10.21.1 SPI_CONFIG ....................................................................................................... 585

10.21.2 SPI_STATUS .......................................................................................................587

10.21.3 SPI_INTR .............................................................................................................589

10.21.4 SPI_INTR_MASK ................................................................................................. 590

10.21.5 SPI_EGRESS_DATA ...........................................................................................591

10.21.6 SPI_INGRESS_DATA .........................................................................................592

10.21.7 SPI_SOCKET ......................................................................................................593

10.21.8 SPI_RX_BYTE_COUNT ......................................................................................594

10.21.9 SPI_TX_BYTE_COUNT ......................................................................................595

10.21.10 SPI_ID ..................................................................................................................596

EZ-USB FX3 Technical Reference Manual., Spec No.: 001-76074 Rev. *D 17

Contents

10.21.11 SPI_POWER ........................................................................................................597

10.22 General Purpose IO Block Registers....................................................................................598

10.22.1 GPIO_SIMPLE .....................................................................................................598

10.22.2 GPIO_INVALUE0 .................................................................................................600

10.22.3 GPIO_INVALUE1 .................................................................................................601

10.22.4 GPIO_INTR0 ........................................................................................................602

10.22.5 GPIO_INTR1 ........................................................................................................603

10.22.6 GPIO_INTR ..........................................................................................................604

10.22.7 GPIO_ID ...............................................................................................................605

10.22.8 GPIO_POWER .....................................................................................................606

10.23 General Purpose IO Registers (one pin) ..............................................................................607

10.23.1 PIN_STATUS .......................................................................................................607

10.23.2 PIN_TIMER ..........................................................................................................609

10.23.3 PIN_PERIOD .......................................................................................................610

10.23.4 PIN_THRESHOLD ...............................................................................................611

10.24 Low Performance Peripherals Registers ..............................................................................612

10.24.1 LPP_ID .................................................................................................................612

10.24.2 LPP_POWER .......................................................................................................613

10.25 DMA Socket and Descriptor Registers .................................................................................614

10.25.1 SCK_DSCR ..........................................................................................................614

10.25.2 SCK_SIZE ............................................................................................................616

10.25.3 SCK_COUNT .......................................................................................................617

10.25.4 SCK_STATUS ......................................................................................................618

10.25.5 SCK_INTR ...........................................................................................................621

10.25.6 SCK_INTR_MASK ...............................................................................................623

10.25.7 DSCR_BUFFER ...................................................................................................625

10.25.8 DSCR_SYNC .......................................................................................................626

10.25.9 DSCR_CHAIN ......................................................................................................628

10.25.10 DSCR_SIZE .........................................................................................................629

10.25.11 EVENT .................................................................................................................631

10.26 DMA Adapter Global Registers.............................................................................................632

10.26.1 SCK_INTR ...........................................................................................................632

10.26.2 ADAPTER_STATUS ............................................................................................638

10.26.3 SIB_ID ..................................................................................................................639

10.26.4 SIB_POWER ........................................................................................................640

10.26.5 SDMMC_CMD_IDX .............................................................................................641

10.26.6 SDMMC_CMD_ARG0 ..........................................................................................642

10.26.7 SDMMC_CMD_ARG1 ..........................................................................................643

10.26.8 SDMMC_RESP_IDX ............................................................................................644

10.26.9 SDMMC_RESP_REG0 ........................................................................................645

10.26.10 SDMMC_RESP_REG1 ........................................................................................646

10.26.11 SDMMC_RESP_REG2 ........................................................................................647

10.26.12 SDMMC_RESP_REG3 ........................................................................................648

10.26.13 SDMMC_RESP_REG4 ........................................................................................649

10.26.14 SDMMC_CMD_RESP_FMT ................................................................................650

10.26.15 SDMMC_BLOCK_COUNT ...................................................................................651

10.26.16 SDMMC_BLOCK_LEN ........................................................................................652

10.26.17 SDMMC_MODE_CFG .........................................................................................653

EZ-USB FX3 Technical Reference Manual., Spec No.: 001-76074 Rev. *D 19

1. Introduction to EZ-USB FX3

EZ-USB® FX3™ is Cypress's high-bandwidth USB 3.0 peripheral controller that provides integrated and flexible features.

FX3 integrates the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for

powerful data processing and for building custom USB SuperSpeed applications.

To provide high-bandwidth access to USB 3.0 data, FX3 contains a hardware unit called General Programmable Interface,

Generation 2 (GPIF II). GPIF II is an enhanced version of the GPIF in FX2LP™, Cypress's USB 2.0 product. GPIF II provides

easy and glueless connectivity to popular interfaces such as asynchronous SRAM and asynchronous and synchronous

address and data multiplexed interfaces. FX3 implements a DMA-centric architecture that enables direct 375-MBps data

transfer from GPIF II to the USB interface without CPU intervention.

An integrated USB 2.0 USB On-The-Go (OTG) controller enables applications in which FX3 may serve dual high-speed roles;

for example, EZ-USB FX3 may function as a High-Speed On-The-Go (HS-OTG) host to USB Mass Storage Class (MSC)

devices and HID-class devices. FX3 contains 512 KB or 256 KB of on-chip SRAM for code and data. EZ-USB FX3 also

provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S. FX3 comes with application

development tools. The software development kit (SDK) provides application examples for accelerating the time to market.

FX3 complies with the USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It also complies with the

Battery Charging Specification v1.1 and USB 2.0 OTG Specification v2.0.

In addition to these features, FX3S has an integrated storage controller and can support up to two independent mass storage

devices. It can support SD 3.0 and eMMC 4.41 memory cards. It can also support SDIO on these ports.

This TRM describes the following functional blocks of the FX3/FX3S device: CPU subsystem, memory, global control, DMA,

USB, GPIF II, low-bandwidth (serial and GPIO) peripherals, and storage (storage block is specific to FX3S only). Registers

associated with these functional blocks are documented in the Registers chapter on page 235.

The following sections describe the details of USB 3.0 and briefly outline the EZ-USB FX3/FX3S architecture.

1.1 Overview of USB 3.0

This section gives an overview of USB 3.0 and describes the significant changes in each layer from the USB 2.0 specification,

including the new power management features provided in USB 3.0. Refer to AN57294 - USB 101: An Introduction to

Universal Serial Bus 2.0 for more details on USB 2.0. The USB 2.0 and 3.0 specifications can be downloaded from

http://www.usb.org/developers/docs.

The USB 3.0 specification, released in 2008, allows a maximum signaling rate of 5 Gbps (SuperSpeed), which is 10 times the

signaling rate of High Speed. The USB 3.0 architecture contains three layers: the physical layer, the link layer on top of the

physical layer, and the protocol layer on top of the link layer.

The additional bandwidth provided by USB SuperSpeed transactions can benefit applications like real-time audio and video

streaming that require a higher bus bandwidth at regular intervals. Mass storage applications can also benefit from the

SuperSpeed bandwidth. FX3 has also been used to implement a high-performance PC-based logic analyzer.

1.1.1 Physical Layer

The physical layer refers to the PHY part of the port and the cable connecting the upstream and downstream ports. USB 3.0

cables have separate shielded differential pairs of lines for transmitting and receiving data. These lines exist along with the

USB 2.0 signals. So a USB 3.0 cable contains a total of nine wires including the four wires that are part of the USB 2.0 cable

20 EZ-USB FX3 Technical Reference Manual., Spec No.: 001-76074 Rev. *D

(see Figure 1-1). The SuperSpeed bus employs a dual-simplex approach that allows simultaneous transmission and

reception of packets. In many cases, a SuperSpeed device may be both transmitting and receiving data at the same time. For

example, during burst transactions, a device may be receiving data from the host and returning acknowledgements

associated with the data it already received.

Figure 1-1. Cross-Section of a USB 3.0 Cable

Coming to the power distribution via the USB 3.0 host, 150 mA is considered as the unit load. USB 3.0 host supplies one unit

load of current for unconfigured devices and six unit loads of current for configured devices. The USB 3.0 host detects the

device connection based on the receiver end termination, and the transmitter is responsible for detecting the device

connection. USB 3.0 uses spread-spectrum clocking on its signaling. If spread-spectrum clocking is enabled, then the energy

of the signal is spread over a larger frequency band rather concentrated over a small frequency band at a high level, helping

to reduce the EMI emissions. The USB 3.0 physical layer supports low-frequency periodic signaling (LFPS), which is used to

manage signal initiation and low-power management on the bus on an idle link to consume less power. Table 1-1 lists the

differences between the USB 3.0 and USB 2.0 physical layers.

Table 1-1. Differences Between Physical Layers of USB 3.0 and USB 2.0

1.1.2 Link Layer

The link layer is responsible for maintaining a reliable and robust communication channel between the host and the device.

The Link Training and Status State Machine (LTSSM) at the core of the USB 3.0 link layer establishes the link connectivity

Feature USB 3.0 USB 2.0

Signaling rate 5 Gbps 480 Mbps

Data transfers Dual simplex Half duplex

Number of pins in the USB cable

9 (VBUS, Ground, D+, D-, SSRX+, SSRX-, SSTX+, SSTX-,

Ground_Drain)

4 (VBUS, Ground, D+, D-)

Data lines in the cable Shielded differential pair (SDP, twisted, or twinax) Unshielded twisted pair (UTP)

Current supplied by the host

150 mA for unconfigured devices, 900 mA for configured

devices

100 mA for unconfigured devices, 500 mA for con-

figured devices

Device detection by the host Receiver end termination Pull-up resistor on D+ or D- lines

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