从MIPS到ARM的迁移指南

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"《从MIPS迁移到ARM》是ARM公司发布的一份技术应用文档，旨在帮助具有MIPS架构背景的开发者顺利过渡到ARM平台。这份文档首次发布于2010年3月，并在后续几个月内进行了修正和补充，提供了关于MIPS到ARM迁移的关键信息和技术指导。" 本文档的主要目标是解决从使用MIPS指令集架构（ISA）到ARM ISA的转换过程中可能遇到的问题和挑战。MIPS和ARM都是常见的处理器架构，广泛应用于嵌入式系统、移动设备和服务器等领域。MIPS以其高效能和低功耗而知名，而ARM则以其广泛的生态系统和灵活性著称。在介绍部分，文档可能涵盖了以下关键知识点： 1. **架构差异**：MIPS和ARM的体系结构基础，包括它们的指令集设计、寻址模式、寄存器配置以及处理流程的不同。 2. **软件兼容性**：如何处理代码移植，包括编译器和链接器的差异，以及二进制兼容性问题。可能涉及重新编译源代码、使用交叉编译工具链等。 3. **硬件接口**：从MIPS到ARM的外设接口变化，例如中断控制器、内存管理单元（MMU）、DMA控制器等，这些都可能需要在固件和驱动程序中进行调整。 4. **性能优化**：分析两种架构的性能特性，讨论如何将MIPS上的优化策略转换为适用于ARM的策略，可能涉及到循环展开、向量化、分支预测等。 5. **操作系统支持**：MIPS和ARM支持的操作系统（如Linux、RTOS等）之间的差异，以及如何迁移和适应新的操作系统环境。 6. **调试与测试**：在新的平台上进行调试的技巧和工具，以及如何确保迁移后的软件质量。 7. **生态系统的转变**：ARM庞大的开发者社区和可用资源，包括库、框架、开发工具等，以及如何利用这些资源加速迁移过程。 8. **实例分析**：可能包含具体的代码示例，展示从MIPS代码到ARM代码的转换步骤。 9. **最佳实践**：提供从项目规划到实施的全面指导，包括迁移策略、时间线管理和风险评估。这份文档对于有经验的MIPS开发者来说，是一份宝贵的资源，可以帮助他们理解两个架构间的本质差异，从而有效地将现有系统迁移到ARM平台上，同时保持性能和稳定性。通过深入学习和应用文档中的知识，开发者可以减少迁移过程中的困扰，加快产品上市速度。

ARM architecture features

Applic

ation Note

235

ARM DAI 0235

ARM architecture features

ARM is a 32

bit architecture. As such, it has 32

bit registers, ALU, data paths, address

and data buses. Additionally, in the native ARM instruction set, all instructions are 32 bits

wide.

Individual ARM implementations may

have internal 64

bit paths for performance

reasons.

2.1

ARM architecture versions

The ARM architecture has been through several revisions since its emergence in the mid

1980’s. The most recent version, ARMv7, is implemented in the Cortex range of

processor co

res. The architecture is defined in three “profiles”, the ‘A’ profile or

Application

class processors, ‘R’ for Real

time and ‘M’ for microcontroller devices.

ARMv7

A is currently implemented in the Cortex

A5, Cortex

A8 and Cortex

A9 processors

and supports

fully

featured application class devices capable of running platform

Operating Systems such as Linux, WinCE etc. It provides full virtual memory support and

optional media processing extensions.

ARMv7

R is available in the Cortex

R4 and is targeted as app

lications which require hard,

predictable real

time performance. Devices incorporating a Cortex

R4 processor core are

used, for instanc

e, in engine management systems, hard disk drive controllers and mobile

baseband processors.

ARMv7

M is used in microcont

roller

type devices, principally those based around the

Cortex

M3 core. This profile supports a subset of features in the v7

A and v7

R profiles

aimed at enabling devices which maximize power efficiency and minimize cost. The

architecture incorporates many

features common in the microcontroller world e.g. bit

banding, hardware interrupt pre

emption etc.

2.2

Programmer’s model

The description presented here is standard for the ARMv7

A and ARMv7

A architecture

profiles. The ARMv7

M microcontroller profile has a d

ifferent model for modes and

exceptions.

2.2.1

Standard features

The ARM register set consists of 37 general

purpose registers, 16 of which are usable at

any one time. The subset which is usable is determined by the current operation mode

(see below

In addition to the general purpose registers, the CPSR (Current Program Status Register)

hold current status, operating mode, instruction set state, ALU status flags etc.

Operating modes

The ARM core supports seven operating modes. All of these, with th

e exception of User

mode, are privileged.

Five modes (Supervisor, Undefined, Abort, FIQ and IRQ) are

associated with handling particular types of exception events.

Applications generally run

either in User mode (unprivileged) or System mode (privileged) wi

th the operating system,

if one is used, running in Supervisor mode.

Instruction sets

Current ARM cores may support several instruction sets



The native ARM instruction set, in which all instructions are 32

bit

ARM architecture features

Application Note 235

ARM DAI 0235



The Thumb instru

ction set (introduced in ARM

v4T), in which all instructions are

bit. This provides greatly improved code density.



Java bytecode

–

cores which include the Jazelle

DBX extension are capable of

executing Java bytecode directly in hardware.

The ARM and Thumb instruction sets have both

been extended several times since

their introduction. In particular, the Thumb

2 extension introduces 32

bit instructions

into the 16

bit Thumb instruction set providing greatly increased performance without

compromising the code density benefits of thumb

Of the ARM cores available on the market today, all support the ARM and Thumb

instruction sets as a minimum

, with the exception of ARMv7

M devices which support

only the Thumb

2 instruction set.

Exceptions and interrupts

ARM supports seven basic exceptio

n types. External interrupts are mapped to the FIQ

and IRQ exceptions. Other exceptions are used for external errors (e.g. bus errors),

internal errors (e.g. undefined instructions or memory address translation faults), or

software interrupts (caused synch

ronously by executing an SVC instruction).

Memory architecture

ARM cores have a 32

bit address bus providing a flat 4GB linear address space. Memory

is addressed in bytes and may be accessed as

byte doublewords,

byte words, 2

byte

halfwords or single b

ytes. Configuration options in the core determine the endianness and

alignment

behavior of the memory interface.

More advanced ARM cores implement caches, Tightly Coupled Memory (TCM) regions,

virtual memory and memory protection features.

2.2.2

Advanced feature

Neon and floating point

ARM provides a standard floating point coprocessor, VFP, which exists in several

versions. It is capable of both scalar and vector operations in single and double precision

IEEE 754 floating point.

The Cortex

A cores, which implem

ent the ARMv7

A architecture, may include the Neon

media processing instruction set. If present, this is executed by a separate media

processing engine integrated with the main integer pipeline.

Jazelle

ARM provides two optional methods for acceleration of

Java and other dynamically

compiler languages.

Jazelle

DBX

(Direct Bytecode eX

ecution) which supports execution of a subset of Java

bytecodes in hardware.

Jazelle

RCT

(Runtime Compilation Target) which provides some extended instructions

to improve perfor

mance of Just

Time compilation techniques for

languages like Java, Perl etc.

Memory protection

Many ARM cores incorporate a Memory Protection Unit (MPU) which allows memory to be

partitioned into a number of regions. Each region cab be assigned access p

ermissions

which are policed automatically by the MPU at run

time.

Virtual memory

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