NVM Express 1.2.1 规范详解

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"NVME 1.2.1规范是NVM Express（Non-Volatile Memory Express）的一个版本，它是一个高速接口标准，用于连接计算机系统和非易失性存储设备，如固态硬盘（SSD）。这个规范在2016年6月5日发布，旨在提高存储设备的性能、效率和兼容性。NVM Express 1.2.1的文档可以在NVM Express组织的官方网站上获取。" NVMe（Non-Volatile Memory Express）是一种基于PCIe总线的协议，它设计的目标是充分利用PCIe接口的带宽潜力，降低延迟，并提供高I/O（输入/输出）性能。与传统的SATA接口相比，NVMe能够显著提升SSD的读写速度，缩短数据传输的延迟，这对于大数据处理、云计算和高性能计算等应用至关重要。 NVM Express 1.2.1规范的更新主要集中在以下几个方面： 1. 性能优化：通过增加命令队列深度、并行处理能力以及支持更大的I/O大小，提升了系统的吞吐量和并发性能。这使得多任务环境中的应用性能得到显著改善。 2. 低延迟：NVMe 1.2.1继续致力于减少延迟，通过优化协议栈和命令处理机制，使得数据传输更加迅速，从而提升用户体验。 3. 功耗管理：引入了新的功耗状态和转换机制，允许设备根据工作负载动态调整功耗，从而实现能效的提升。 4. 安全性增强：增加了对加密、数据保护和安全擦除的支持，以确保数据的安全性和隐私。 5. 错误恢复和故障处理：提供了更精细的错误报告和处理机制，增强了系统的稳定性和可靠性。 6. 兼容性和扩展性：NVMe 1.2.1规范确保了不同厂商设备之间的互操作性，并为未来的存储技术发展预留了空间，比如对新类型存储介质的支持。 7. 热插拔和管理功能：改进了热插拔支持，允许在系统运行时添加或移除存储设备，同时增强了设备管理和监控功能。 8. 软件栈改进：包括对操作系统驱动程序和用户空间应用程序接口的改进，简化了软件开发和部署过程。对于NVM Express成员，他们有权按照公司的知识产权政策和章程实施此规范。而非成员则只能查看和引用此文档，但必须承认NVM Express作为原始来源。总而言之，NVMe 1.2.1规范是存储技术领域的一个重要里程碑，它推动了存储设备性能的提升，降低了延迟，提高了系统效率，同时也为数据中心、服务器和高性能计算环境提供了更强大的存储解决方案。随着技术的不断进步，NVMe规范的后续版本还将持续优化和扩展，以满足不断增长的存储需求。

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NVM Express 1.2.1

1.6.3 arbitration mechanism

The method used to determine which Submission Queue is selected next to launch commands for

execution by the controller. Three arbitration mechanisms are defined including round robin, weighted round

robin with urgent priority class, and vendor specific. Refer to section 4.11.

1.6.4 candidate command

A candidate command is a submitted command the controller deems ready for processing.

1.6.5 command completion

A command is completed when the controller has completed processing the command, has updated status

information in the completion queue entry, and has posted the completion queue entry to the associated

Completion Queue.

1.6.6 command submission

A command is submitted when a Submission Queue Tail Doorbell write has completed that moves the

Submission Queue Tail Pointer value past the corresponding Submission Queue entry for the associated

command.

1.6.7 controller

A PCI Express function that implements NVM Express.

1.6.8 extended LBA

An extended LBA is a larger LBA that is created when metadata associated with the LBA is transferred

contiguously with the LBA data. Refer to Figure 213.

1.6.9 firmware slot

A firmware slot is a location in the controller used to store a firmware image. The controller stores between

one and seven firmware images. When downloading new firmware to the controller, host software has the

option of specifying which image is replaced by indicating the firmware slot number.

1.6.10 I/O command

An I/O command is a command submitted to an I/O Submission Queue.

1.6.11 I/O Completion Queue

An I/O Completion Queue is a Completion Queue that is used to indicate command completions and is

associated with one or more I/O Submission Queues. I/O Completion Queue identifiers are from 1 to

65535.

1.6.12 I/O Submission Queue

An I/O Submission Queue is a Submission Queue that is used to submit I/O commands for execution by

the controller (e.g. Read, Write for the NVM command set). I/O Submission Queue identifiers are from 1

to 65535.

1.6.13 LBA range

A collection of contiguous logical blocks specified by a starting LBA and number of logical blocks.

1.6.14 logical block

The smallest addressable data unit for Read and Write commands.

1.6.15 logical block address (LBA)

The address of a logical block, referred to commonly as LBA.

1.6.16 metadata

Metadata is contextual information about a particular LBA of data. The host may include metadata to be

stored by the NVM subsystem if storage space is provided by the controller.

NVM Express 1.2.1

1.6.17 Namespace

A quantity of non-volatile memory that may be formatted into logical blocks. When formatted, a namespace

of size n is a collection of logical blocks with logical block addresses from 0 to (n-1).

1.6.18 Namespace ID (NSID)

An identifier used by a controller to provide access to a namespace. Refer to section 6.1 for the definitions

of valid NSID, invalid NSID, active NSID, inactive NSID, allocated NSID, and unallocated NSID.

1.6.19 NVM

NVM is an acronym for non-volatile memory.

1.6.20 NVM subsystem

An NVM subsystem includes one or more controllers, one or more namespaces, one or more PCI Express

ports, a non-volatile memory storage medium, and an interface between the controller(s) and non-volatile

memory storage medium.

1.6.21 private namespace

A namespace that is accessible by only one controller. A host may determine whether a namespace is a

private namespace or may be a shared namespace by the value of the Namespace Multi-path I/O and

Namespace Sharing Capabilities (NMIC) field in the Identify Namespace data structure.

1.6.22 Runtime D3 (Power Removed)

In Runtime D3 (RTD3) main power is removed from the controller. Auxiliary power may or may not be

provided.

1.6.23 shared namespace

A namespace that is accessible by two or more controllers in an NVM subsystem. A host may determine

whether a namespace is a private namespace or may be a shared namespace by the value of the

Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC) field in the Identify Namespace

data structure.

1.7 Keywords

Several keywords are used to differentiate between different levels of requirements.

1.7.1 mandatory

A keyword indicating items to be implemented as defined by this specification.

1.7.2 may

A keyword that indicates flexibility of choice with no implied preference.

1.7.3 optional

A keyword that describes features that are not required by this specification. However, if any optional

feature defined by the specification is implemented, the feature shall be implemented in the way defined by

the specification.

1.7.4 R

“R” is used as an abbreviation for “reserved” when the figure or table does not provide sufficient space for

the full word “reserved”.

1.7.5 reserved

A keyword referring to bits, bytes, words, fields, and opcode values that are set-aside for future

standardization. Their use and interpretation may be specified by future extensions to this or other

specifications. A reserved bit, byte, word, field, or register shall be cleared to zero, or in accordance with a

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