![](https://csdnimg.cn/release/download_crawler_static/12143375/bg10.jpg)
1810 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 6, JUNE 2019
[4] S. Lee et al., “A 128 Gb 2b/cell NAND flash memory in 14 nm
technology with tPROG=640 µs and 800 MB/s I/O rate,” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco,
CA, USA, Jan./Feb. 2016, pp. 138–139.
[5] S. Lee, “Scaling challenges in NAND flash device toward 10nm technol-
ogy,” in Proc. 4th IEEE Int. Memory Workshop, Milan, Italy, May 2012,
pp. 1–4.
[6] K. Takeuchi, “Scaling challenges of NAND flash memory and hybrid
memory system with storage class memory & NAND flash memory,” in
Proc. IEEE Custom Int. Circuits Conf., San Jose, CA, USA, Sep. 2013,
pp. 1–6.
[7] Y. Fukuzumi et al., “Optimal integration and characteristics of ver-
tical array devices for ultra-high density, bit-cost scalable flash
memory,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2007,
pp. 449–452.
[8] K.-T. Park et al., “Three-dimensional 128 Gb MLC vertical nand
flash memory with 24-WL stacked layers and 50 MB/s high-
speed programming,” IEEE J. Solid-State Circuits, vol. 50, no. 1,
pp. 204–213, Jan. 2015.
[9] R. Micheloni, S. Aritome, and L. Crippa, “Array architectures for 3-D
NAND flash memories,” Proc. IEEE, vol. 105, no. 9, pp. 1634–1649,
Sep. 2017.
[10] T. Tanaka et al., “A 768Gb 3b/cell 3D-floating-gate NAND
flash memory,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, San Francisco, CA, USA, Jan./Feb. 2016,
pp. 142–143.
[11] R. Yamashita et al., “A 512Gb 3b/cell flash memory on 64-word-
line-layer BiCS technology,” in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2017,
pp. 196–197.
[12] C. Kim et al., “A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash
memory,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, San Francisco, CA, USA, Feb. 2017, pp. 202–203.
[13] H.-J. Kang et al., “Comprehensive analysis of retention characteristics
in 3-D NAND flash memory cells with tube-type poly-Si channel
structure,” in Proc. Symp. VLSI Technol., Kyoto, Japan, Jun. 2015,
pp. T182–T183.
[14] D. Oh et al., “TCAD simulation of data retention characteristics of
charge trap device for 3-D NAND flash memory,” in Proc. IEEE
Int. Memory Workshop (IMW), Monterey, CA, USA, May 2015,
pp. 1–4.
[15] B. Choi et al., “Comprehensive evaluation of early retention (fast charge
loss within a few seconds) characteristics in tube-type 3-D NAND flash
memory,” in Proc. IEEE Symp. VLSI Technol., Honolulu, HI, USA,
Jun. 2016, pp. 1–2.
[16] K. Mizoguchi, T. Takahashi, S. Aritome, and K. Takeuchi, “Data-
retention characteristics comparison of 2D and 3D TLC NAND flash
memories,” in Proc. IEEE Int. Memory Workshop, Monterey, CA, USA,
May 2017, pp. 1–4.
[17] K. Mizoguchi, S. Kotaki, Y. Deguchi, and K. Takeuchi, “Lateral charge
migration suppression of 3D-NAND flash by vth nearing for near data
computing,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2017,
pp. 19.2.1–19.2.4.
[18] T. Nakamura, Y. Deguchi, and K. Takeuchi, “AEP-LDPC ECC with error
dispersion coding for burst error reduction of 2D and 3D NAND flash
memories,” in Proc. IEEE Int. Memory Workshop (IMW), Monterey, CA,
USA, May 2017, pp. 1–4.
[19] C. Zambelli et al., “Characterization of TLC 3D-NAND flash endurance
through machine learning for LDPC code rate optimization,” in
Proc. IEEE Int. Memory Workshop, Monterey, CA, USA, May 2017,
pp. 1–4.
[20] Y. Lee, H. Yoo, J. Jung, J. Jo, and I.-C. Park, “A 2.74-pJ/bit, 17.7-Gb/s
iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash
memory,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2531–2540,
Oct. 2013.
[21] G. Dong, N. Xie, and T. Zhang, “On the use of soft-decision error-
correction codes in nand flash memory,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 58, no. 2, pp. 429–439, Feb. 2011.
[22] C.-L. Chen, K.-S. Lin, H.-C. Chang, W.-C. Fang, and C.-Y. Lee,
“A 11.5-Gbps LDPC decoder based on CP-PEG code con-
struction,” in Proc. ESSCIRC, Athens, Greece, Sep. 2009,
pp. 412–415.
[23] C. Matsui, R. Kinoshita, and K. Takeuchi, “Analysis on applicable error-
correcting code strength of storage class memory and NAND flash in
hybrid storage,” Jpn. J. Appl. Phys., vol. 57, no. 4S, Feb. 2018, Art.
no. 04FE01.
[24] S. Tanakamaru, Y. Yanagihara, and K. Takeuchi, “Error-prediction
LDPC and error-recovery schemes for highly reliable solid-state drives
(SSDs),” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2920–2933,
Nov. 2013.
[25] T. Tokutomi, M. Doi, S. Hachiya, A. Kobayashi, S. Tanakamaru, and
K. T. Vi, “Enterprise-grade 6x fast read and 5x highly reliable SSD with
TLC NAND-flash memory for big-data storage,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA,
Feb. 2015, pp. 1–3.
[26] C. A. Aslam, Y. L. Guan, and K. Cai, “Retention-aware belief-
propagation decoding for NAND flash memory,” IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 64, no. 6, pp. 725–729,
Jun. 2017.
[27] T. Takahashi, S. Yamazaki, and K. Takeuchi, “Data-retention time
prediction of long-term archive SSD with flexible-nLC NAND flash,”
in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Pasadena, CA, USA,
Apr. 2016, pp. 6C-5-1–6C-5-6.
[28] OpenFace. Accessed: Mar. 4, 2019. [Online]. Available:
https://cmusatyalab.github.io/openface/
[29] Y. Li et al., “128 Gb 3b/cell NAND Flash Memory in 19 nm technology
with 18 MB/s write rate and 400 Mb/s toggle mode,” in Proc. IEEE
Int. Solid-State Circuits Conf., San Francisco, CA, USA, Feb. 2012,
pp. 436–437.
[30] J.-W. Im et al., “A 128 Gb 3b/cell V-NAND flash memory with 1 Gb/s
I/O rate,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, San Francisco, CA, USA, Feb. 2015, pp. 1–3.
[31] S. Tanakamaru, C. Hung, and K. Takeuchi, “Highly reliable and low
power SSD using asymmetric coding and stripe bitline-pattern elim-
ination programming,” IEEE J. Solid-State Circuits, vol. 47, no. 1,
pp. 85–96, Jan. 2012.
[32] Y. Deguchi, A. Kobayashi, H. Watanabe, and K. Takeuchi, “Flash
reliability boost Huffman coding (FRBH): Co-optimization of data
compression and V
th
distribution modulation to enhance data-retention
time by over 2900x,” in Proc. Symp. VLSI Technol., Kyoto, Japan,
Jun. 2017, pp. T206–T207.
[33] Y. Deguchi and K. Takeuchi, “Word-line batch V
th
modulation of TLC
NAND flash memories for both write-hot and cold data,” in Proc.
IEEE Asian Solid-State Circuits Conf. (A-SSCC), Seoul, South Korea,
Nov. 2017, pp. 161–164.
[34] N. P. Jouppi et al., “In-datacenter performance analysis of a tensor
processing unit,” in Proc. ACM/IEEE 44th Annu. Int. Symp. Comput.
Archit. (ISCA), Toronto, ON, Canada, Jun. 2017, pp. 1–12.
[35] Z. Cai, X. He, J. Sun, and N. Vasconcelos, “Deep learning with low
precision by half-wave Gaussian quantization,” in Proc. IEEE Conf.
Comput. Vis. Pattern Recognit. (CVPR), Honolulu, HI, USA, Jul. 2017,
pp. 5406–5414.
Yoshiaki D eguch i (M’17) received the B.E. and
M.E. degrees from the Department of Electrical,
Electric, and Communication Engineering, Chuo
University, Tokyo, Japan, in 2016 and 2018,
respectively.
He is currently a Visiting Researcher with Chuo
University. He is also currently with Hitachi
Ltd. Research and Development Group, Yokohama,
Japan. He has been engaged in research on reliabil-
ity enhancement techniques, error-correcting codes
(ECCs), data compression techniques, and approxi-
mate computing for
NAND flash memory-based SSD.
Toshiki Nakamura received the B.E. degree from
the Department of Electrical, Electric, and Com-
munication Engineering, Chuo University, Tokyo,
Japan, in 2017, where he is currently pursuing the
M.S. degree.
He has been engaged in a research on reliability
of
NAND flash memory.