同一网络下的以太网重定时器：TI-DS110DF410.pdf产品简介

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描述： TI-DS110DF410.pdf，是关于以太网重定时器的技术手册。本手册包含了关于TI-DS110DF410以太网重定时器的详细介绍、技术规格以及应用示例等内容。本文将对TI-DS110DF410以太网重定时器的功能、性能、应用等方面进行全面解析，以帮助读者更好地理解和使用该产品。首先，本手册首先介绍了以太网重定时器的背景和重要性。随着以太网的普及和应用范围的不断扩大，以太网的时钟同步问题变得越来越重要。TI-DS110DF410以太网重定时器作为一种专门设计用于解决以太网时钟同步问题的器件，可以有效地提供精确的时钟同步功能，从而提高网络的性能和可靠性。接着，本手册详细介绍了TI-DS110DF410以太网重定时器的功能和特点。该器件采用了先进的时钟同步技术，可以实现高精度和低抖动的时钟同步。其具有多种接口和协议支持，适用于各种以太网应用场景。此外，TI-DS110DF410还具有低功耗和高可靠性等优点，适用于各种工业和商业应用。随后，本手册详细介绍了TI-DS110DF410以太网重定时器的技术规格和性能参数。包括工作电压范围、时钟频率范围、时钟同步精度等。此外，还介绍了其功耗、温度范围和可靠性等方面的指标。这些技术规格和性能参数可以帮助用户选择合适的器件，并确保其在特定应用场景下的性能和可靠性。然后，本手册还提供了一些TI-DS110DF410以太网重定时器的应用示例。这些示例包括网络交换机、路由器、工业自动化和数据中心等应用场景。对于每个应用场景，本手册给出了详细的电路连接图和参数配置建议，以帮助用户快速上手并实现理想的时钟同步效果。最后，本手册还包括了TI-DS110DF410以太网重定时器的使用指南和注意事项。其中包括器件的安装步骤、配置方法以及常见问题的解决方法等。这些指南和注意事项可以帮助用户正确、稳定地使用TI-DS110DF410，并充分发挥其在时钟同步方面的优势。综上所述，TI-DS110DF410.pdf是一本关于以太网重定时器的详细技术手册。通过对该手册的阅读和理解，读者可以全面了解TI-DS110DF410以太网重定时器的功能、性能和应用方面的知识，并能够正确、稳定地使用该器件，从而提高网络的性能和可靠性。无论是工程师还是研究人员，本手册都是一个宝贵的参考资料，能够帮助他们在以太网时钟同步方面取得更好的成果。

0.2

0.4

0.6

0.8

1.2

-40 -20 0 20 40 60 80

Voltage Output Differential (Vp-p)

Temperature (degrees C)

VOD = 0.6Vpp

VOD = 0.8Vpp

VOD = 1.0Vpp

VOD = 1.2Vpp

C00

0.2

0.4

0.6

0.8

1.2

-40 -20 0 20 40 60 80

Voltage Output Differential (Vp-p)

Temperature (degrees C)

VOD = 0.6Vpp

VOD = 0.8Vpp

VOD = 1.0Vpp

VOD = 1.2Vpp

C00

DS110DF410

www.ti.com.cn

ZHCSDP9D –OCTOBER 2011–REVISED APRIL 2015

7.6 Typical Characteristics

Figure 1. Typical VOD vs VDD Figure 2. Typical VOD vs Temperature

DS110DF410

www.ti.com.cn

ZHCSDP9D –OCTOBER 2011–REVISED APRIL 2015

Feature Description (continued)

Once the CDR has locked and the CTLE has been adapted, the CTLE boost level will be frozen until a manual

re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE is typically

readapted by resetting the CDR.

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-

boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost

combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel

registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost

settings.

CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost

combinations that sum to the same number will have approximately the same boost level, but will result in a

different shape for the EQ transfer function (boost curve).

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather

than a linear stage. This is useful in some applications, but it should not be typically used in combination with the

DFE.

8.3.4 DFE

A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of cross talk,

reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the

selected adapt mode. The DFE can be manually configured to specified tap polarities and tap weights.

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity

bit.

8.3.5 Clock and Data Recovery

The DS110DF410 performs its clock and data recovery function by detecting the bit transitions in the incoming

data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit

transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the

bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS110DF410 in a

system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the

system.

The DS110DF410 uses the 25 MHz reference to determine the coarse tuning setting for its internal VCO. On

power-up, on CDR reset, and when the DS110DF410 loses lock and cannot re-acquire lock after four attempts,

the 25 MHz reference is used to calibrate the VCO frequency. The required VCO frequency is set by using the

rate/subrate settings (see Table 2) or by manually setting the PPM count and divide ratio. To calibrate the VCO

frequency, the DS110DF410 searches through the available VCO coarse tuning settings and counts the divided

VCO frequency using the 25 MHz reference as a clock source. The VCO coarse tuning setting which provides

the VCO frequency closest to the required frequency is stored, and this coarse tuning setting is used for

subsequent operation. This produces a fast, robust phase lock to the input signal.

8.3.6 Output Driver

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis.

The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The

DS110DF410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user

is responsible for configuring these parameters. They can be set for each channel independently.

An idealized transmit waveform with analog de-emphasis applied is shown in Figure 4.

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