"TI-DS110DF111.pdf: 以太网重定时器设计与接口指南"

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TI-DS110DF111.pdf is a datasheet for the DS110DF111, an Ethernet retimer chip designed to improve signal integrity in high-speed networking applications. The chip features VDDOUTA and POUTA_N, as well as INB_PINB and NSCLADDR0/LOCKSDAINA_PINA_NOUTB_POUTB_N. In addition, the datasheet provides details on the recommended power supply configuration, including the use of 100nF and 25 MHz components. The DS110DF111 operates at a voltage of 3.3V and has a capacitance of 0.22μF (2x). The datasheet also outlines the pin assignments, including REFCLK_INEN_SMBGND and various 1kΩ and 2kΩ components. Additionally, the datasheet includes information on ADDR1/VODB/DONE and other key features of the DS110DF111. In conclusion, the TI-DS110DF111.pdf datasheet provides comprehensive information on the DS110DF111 Ethernet retimer chip, including its key features, pin assignments, power supply recommendations, and other important details for designers and engineers working on high-speed networking applications.

Frequency (MHz)

-6

-5

-4

-3

-2

-1

0 1000 2000 3000 4000 5000

-1.5

-3.5

-6

De-Emphasis (dB)

DS110DF111

www.ti.com.cn

ZHCSDW7A –MAY 2013–REVISED JUNE 2015

6.6 Typical Characteristics

Test Conditions

Datarate: 10.3125 Gbps with a PRBS7 pattern

Jitter Measurements

VOD Setting: 1000mV

Rj (RMS): 315 fs Dj: 3.74 ps Tj (1E-12): 7.33 ps

Temperature: 25°C and VDD = 2.5V

Figure 5. Output Eye Diagram 10.3125 Gbps

Figure 4. De-Emphasis Gain vs. Frequency

Loopback IN

OUT

LOS

Channel

Status

and

Control

LOCK

SMBus

PRBS9

PRBS31

DFE

Polarity DE VOD

VCO

CDR

CTLE

Signal

Detect

Eye

Monitor

Loopback OUT

Raw

Retimed

DS110DF111

ZHCSDW7A –MAY 2013–REVISED JUNE 2015

www.ti.com.cn

7 Detailed Description

7.1 Overview

The DS110DF111 is a low-power, multirate, 2-channel retimer. Both channels operate independently. Each

channel includes a Continuous Time Linear Equalizer (CTLE) which compensates for the presence of a

dispersive transmission channel between the source and the input of the DS110DF111. Each channel includes

an independent Voltage-Controlled Oscillator (VCO) and Phase-Locked Loop (PLL) which produce a clean clock.

The clean clock produced by the VCO and the PLL is phase-locked to the incoming data clock, but the high-

frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially reduced

jitter. This clean clock is used to retime the incoming data, removing high-frequency jitter from the data stream

and producing a data output signal with reduced jitter. This provides the Clock and Data Recovery (CDR)

function of the retimer.

Each channel of the DS110DF111 features an output driver with settable differential output voltage and settable

output de-emphasis. The output de-emphasis compensates for dispersion in the transmission channel at the

output of the DS110DF111.

7.2 Functional Block Diagram

Figure 6. DS110DF111 Data Path Block Diagram

7.3 Feature Description

7.3.1 Device Data Path Operation

The data path operation of the DS110DF111 is shown Figure 6. The functional sections are as follows.

• Input Channel Equalization

• Clock and Data Recovery

• PRBS Pattern Generator

• Datapath Multiplexer and Output Driver

• Reference Clock

• Control Pins

• Eye Opening Monitor

7.3.1.1 Input Channel Equalization

Physical transmission media comprising traces on printed circuit boards (PCBs) or copper cables exhibit a low-

pass frequency response characteristic. The magnitude of the high frequency loss varies with the length of the

transmission medium and with the loss of the materials which comprise it. This differential high frequency loss

and the frequency-dependent group delay of the transmission medium introduce inter-symbol interference in the

high-speed broadband signals propagating through the transmission medium.

DS110DF111

www.ti.com.cn

ZHCSDW7A –MAY 2013–REVISED JUNE 2015

Feature Description (continued)

To make configuration of these settings easier, the DS110DF111 is designed to determine the correct settings

for the CTLE autonomously by automatically adapting these equalizations to the input transmission medium. The

automatic adaptation takes place when a signal is first detected at the input to the DS110DF111, immediately

after the DS110DF111 acquires phase lock.

The automatic adaptation is also triggered whenever the CDR circuitry is reset. The DS110DF111 uses its

internal eye monitor to generate a figure of merit for the adaptation. The DS110DF111 adjusts its CTLE boost

settings in a systematic way to optimize this figure of merit. When 8b/10b encoding is used and the input

channels has more than 15 dB of loss, the CTLE table and or adaption algorithm needs to be modified so as to

prevent CTLE mal-adaption. This scenario occurs when the CTLE boost is insufficient at lower settings to cause

regeneration of the high-frequency content of the K28.5 pattern. As boost is increased, the adaption Figure of

Merit (FOM) temporarily observes eye closure as the EQ boost begins to restore the high-frequency content. If

the FOM does not improve within the look-beyond counter depth, the CTLE will settle at a lower boost, which is

insufficient to equalize the signal and provide good BER.

The 5-tap DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the

DS110DF111. The DFE tap weights and polarities are adaptive and operate in conjunction with the CTLE to

achieve an acceptable BER with more severe channel impairments.

7.3.1.2 Clock And Data Recovery

The DS110DF111 performs its clock and data recovery function by detecting the bit transitions in the incoming

data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit

transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the

bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS110DF111 in a

system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the

system.

7.3.1.3 PRBS Pattern Generator

Each channel in the DS110DF111 can be configured to generate and output its own pseudo random bit

sequence (PRBS). The DS110DF111 pattern generators support the following PRBS sequences:

• PRBS-9, 2

- 1

• PRBS-31, 2

- 1

7.3.1.4 Datapath Multiplexer and Output Driver

The DS110DF111 datapath multiplexer is used to control which internal signal will be presented to the output

driver block. Inputs to this multiplexer include raw equalized data without clock recovery, retimed data, PRBS

patterns, and Loopback data from the other datapath.

The DS110DF111 output driver is used to control specific signal characteristics to enhance transmission quality.

The output driver is used to control the following signal features

• Amplitude

• De-Emphasis

• Edge Rate

• Polarity

The DS110DF111 is commonly used in applications where lossy transmission media exist both at the input and

the output of the DS110DF111. The CTLE compensates for lossy transmission media at the input to the

DS110DF111. The output de-emphasis compensates for the lossy transmission medium at the output of the

DS110DF111.

When there is a transition in the output data stream, the output differential voltage reaches its configured

maximum value within the configured rise/fall time of the output driver. Following this, the differential voltage

rapidly falls off until it reaches the configured VOD level minus the configured de-emphasis level. This

accentuates the high-frequency components of the output driver signal at the expense of the low frequency

components. The pre-distorted DS110DF111 output signal, with high-frequency components emphasized relative

to its low frequency components, exhibits less inter-symbol interference after traveling down a dispersive

transmission medium than an undistorted output signal.

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