MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 2
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
24.1 QUICC Engine Block .................................................................................................... 24-1
24.2 QUICC Engine Implementation Details for the MPC8309........................................... 24-2
24.2.1 System Interface ........................................................................................................ 24-4
24.2.2 Configuration – Parameter RAM............................................................................. 24-35
24.2.3 QUICC Engine Multiplexing and Timers................................................................ 24-40
24.2.4 UCC Ethernet (UEC)............................................................................................... 24-43
24.2.5 IEEE Standard 1588 Assist...................................................................................... 24-43
Appendix A
Complete List of Configuration, Control, and Status Registers
A.1 Local Access Windows.................................................................................................... 1-1
A.2 System Configuration Registers ...................................................................................... 1-2
A.3 Watchdog Timer (WDT).................................................................................................. 1-3
A.4 Real Time Clock (RTC) ................................................................................................... 1-4
A.5 Periodic Interval Timer (PIT) .......................................................................................... 1-4
A.6 General Purpose (Global) Timers (GTMs)...................................................................... 1-4
A.7 Integrated Programmable Interrupt Controller (IPIC)..................................................... 1-5
A.8 QUICC Engine Ports Interrupts....................................................................................... 1-7
A.9 System Arbiter ................................................................................................................. 1-7
A.10 Reset Configuration .........................................................................................................1-7
A.11 Clock Configuration ........................................................................................................ 1-8
A.12 Power Management Controller (PMC)............................................................................ 1-8
A.13 General Purpose I/O (GPIO)............................................................................................ 1-8
A.14 DDR Memory Controller................................................................................................. 1-9
A.15 I
2
C Controller ................................................................................................................ 1-11
A.16 DUART.......................................................................................................................... 1-11
A.17 Enhanced Local Bus Controller (eLBC)........................................................................ 1-12
A.18 Serial Peripheral Interface (SPI).................................................................................... 1-14
A.19 DMA Engine 1............................................................................................................... 1-14
A.20 DMA Engine 2............................................................................................................... 1-15
A.21 Enhanced Secure Digital Host Controller (eSDHC)...................................................... 1-16
A.22 FlexCAN........................................................................................................................ 1-17
A.23 PCI Configuration Access Registers.............................................................................. 1-18
A.24 PCI Memory Mapped Registers .................................................................................... 1-19
A.25 Universal Serial Bus (USB) Interface............................................................................ 1-20
Appendix B
Revision History
B.1 Changes From Revision 1 to Revision 2 ......................................................................... 2-1