CY7C68013A-56PVXI：高速USB2.0接口芯片手册

usb2.0手册

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"该文档是关于CY7C68013A-56PVXI的硬件开发手册，主要涉及高速USB2.0接口的常用芯片CY7C68013A、CY7C68014A、CY7C68015A和CY7C68016A。这是Cypress Semiconductor Corporation生产的EZ-USB FX2LP系列USB微控制器，适用于高速USB外围设备控制器。" CY7C68013A/14A/15A/16A是Cypress Semiconductor推出的一系列高速USB2.0接口芯片，它们都通过了USB Implementers Forum (USB IF)的高速认证，具有TID#40460272的标识。这些芯片集成了USB2.0收发器、智能串行接口引擎(SIE)和增强型8051微处理器，能够在单芯片上实现USB通信的核心功能。在硬件兼容性方面，CY7C68013A系列芯片与FX2系列保持了引脚兼容性、目标代码兼容性和功能兼容性，这意味着它们可以无缝替换FX2系列芯片，而不需要更改硬件设计或大部分软件代码。此外，它们还具备超低功耗特性，任何模式下的电流消耗不超过85mA，这使得它们非常适合电池供电或USB总线供电的应用场景。在软件支持方面，8051微处理器的代码可以在多种存储介质上运行，包括内部RAM（通过USB下载）、内部RAM（从EEPROM加载）以及外部内存设备（在128引脚封装的版本中）。这些芯片内置16KB的片上代码/数据RAM，提供了足够的存储空间来运行应用程序或处理数据。 CY7C68013A系列芯片支持四个可编程的BULK/INTERRUPT/ISOCHRONOUS端点，可以根据需求进行缓冲选项配置，如双缓冲、三缓冲和四缓冲，以优化数据传输效率。此外，还有一个额外的64字节可编程BULK/INTERRUPT端点，进一步扩展了其功能。8位或16位的外部数据接口允许芯片与各种外部设备进行高效交互。该芯片还集成了SmartMedia标准错误校验码(ECC)生成功能，确保数据传输的可靠性。此外，还有通用输入/输出(GP)引脚，可以灵活配置以满足不同应用的需求。总而言之，CY7C68013A系列芯片是一款强大的USB2.0解决方案，结合了高性能、低功耗和高度灵活性，适用于需要高速USB连接的多种嵌入式系统和外围设备开发。通过理解并充分利用其特性，开发者能够构建出高效、可靠的USB2.0应用。

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *M Page 11 of 62

3.12.5 Default Full Speed Alternate Settings

3.12.6 Default High Speed Alternate Settings

3.13 External FIFO Interface

3.13.1 Architecture

The FX2LP slave FIFO architecture has eight 512 byte blocks in

the endpoint RAM that directly serve as FIFO memories and are

controlled by FIFO control signals (such as IFCLK, SLCS#,

SLRD, SLWR, SLOE, PKTEND, and flags).

In operation, some of the eight RAM blocks fill or empty from the

SIE, while the others are connected to the I/O transfer logic. The

transfer logic takes two forms, the GPIF for internally generated

control signals and the slave FIFO interface for externally

controlled transfers.

3.13.2 Master/Slave Control Signals

The FX2LP endpoint FIFOS are implemented as eight physically

distinct 256x16 RAM blocks. The 8051/SIE can switch any of the

RAM blocks between two domains, the USB (SIE) domain and

the 8051-I/O Unit domain. This switching is done virtually instan-

taneously, giving essentially zero transfer time between “USB

FIFOS” and “Slave FIFOS.” Because they are physically the

same memory no bytes are actually transferred between buffers.

At any given time, some RAM blocks are filling/emptying with

USB data under SIE control, while other RAM blocks are

available to the 8051, the I/O control unit or both. The RAM

blocks operate as single port in the USB domain, and dual port

in the 8051-I/O domain. The blocks can be configured as single,

double, triple, or quad buffered as previously shown.

The I/O control unit implements either an internal master (M for

master) or external master (S for Slave) interface.

In Master (M) mode, the GPIF internally controls FIFOADR[1..0]

to select a FIFO. The RDY pins (two in the 56-pin package, six

in the 100-pin and 128-pin packages) can be used as flag inputs

from an external FIFO or other logic if desired. The GPIF can be

run from either an internally derived clock or externally supplied

clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s

(48-MHz IFCLK with 16-bit interface).

In Slave (S) mode, the FX2LP accepts either an internally

derived clock or externally supplied clock (IFCLK, max frequency

48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals

from external logic. When using an external IFCLK, the external

clock must be present before switching to the external clock with

the IFCLKSRC bit. Each endpoint can individually be selected

for byte or word operation by an internal configuration bit and a

Slave FIFO Output Enable signal SLOE enables data of the

selected width. External logic must ensure that the output enable

signal is inactive when writing data to a slave FIFO. The slave

interface can also operate asynchronously, where the SLRD and

SLWR signals act directly as strobes, rather than a clock qualifier

as in synchronous mode. The signals SLRD, SLWR, SLOE and

PKTEND are gated by the signal SLCS#.

Table 6. Default Full Speed Alternate Settings

[4, 5]

Alternate Setting 0 1 2 3

ep0 64 64 64 64

ep1out 0 64 bulk 64 int 64 int

ep1in 0 64 bulk 64 int 64 int

ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)

ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)

ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)

ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)

Notes

4. “0” means “not implemented.”

5. “2×” means “double buffered.”

6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

Table 7. Default High Speed Alternate Settings

[4, 5]

Alternate Setting 0 1 2 3

ep0 64 64 64 64

ep1out 0 512 bulk

[6]

64 int 64 int

ep1in 0 512 bulk

[6]

64 int 64 int

ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×)

ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×)

ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×)

ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)

[+] Feedback

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *M Page 12 of 62

3.13.3 GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the

internally supplied interface clock: 30 MHz and 48 MHz. Alterna-

tively, an externally supplied clock of 5 MHz–48 MHz feeding the

IFCLK pin can be used as the interface clock. IFCLK can be

configured to function as an output clock when the GPIF and

FIFOs are internally clocked. An output enable bit in the

IFCONFIG register turns this clock output off, if desired. Another

bit within the IFCONFIG register inverts the IFCLK signal

whether internally or externally sourced.

3.14 GPIF

The GPIF is a flexible 8-bit or 16-bit parallel interface driven by

a user programmable finite state machine. It enables the

CY7C68013A/15A to perform local bus mastering and can

implement a wide variety of protocols such as ATA interface,

printer parallel port, and Utopia.

The GPIF has six programmable control outputs (CTL), nine

address outputs (GPIFADRx), and six general-purpose ready

inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF

vector defines the state of the control outputs, and determines

what state a ready input (or multiple inputs) must be before

proceeding. The GPIF vector can be programmed to advance a

FIFO to the next data value, advance an address, etc. A

sequence of the GPIF vectors make up a single waveform that

is executed to perform the desired data move between the

FX2LP and the external device.

3.14.1 Six Control OUT Signals

The 100-pin and 128-pin packages bring out all six Control

Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to

define the CTL waveforms. The 56-pin package brings out three

of these signals, CTL0–CTL2. CTLx waveform edges can be

programmed to make transitions as fast as once per clock (20.8

ns using a 48-MHz clock).

3.14.2 Six Ready IN Signals

The 100-pin and 128-pin packages bring out all six Ready inputs

(RDY0–RDY5). The 8051 programs the GPIF unit to test the

RDY pins for GPIF branching. The 56-pin package brings out two

of these signals, RDY0–1.

3.14.3 Nine GPIF Address OUT Signals

Nine GPIF address lines are available in the 100-pin and 128-pin

packages, GPIFADR[8..0]. The GPIF address lines enable

indexing through up to a 512 byte block of RAM. If more address

lines are needed I/O port pins are used.

3.14.4 Long Transfer Mode

In the master mode, the 8051 appropriately sets GPIF trans-

action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or

GPIFTCB0) for unattended transfers of up to 2

transactions.

The GPIF automatically throttles data flow to prevent under or

overflow until the full number of requested transactions

complete. The GPIF decrements the value in these registers to

represent the current status of the transaction.

3.15 ECC Generation

[7]

The EZ-USB can calculate ECCs (Error Correcting Codes) on

data that passes across its GPIF or Slave FIFO interfaces. There

are two ECC configurations: Two ECCs, each calculated over

256 bytes (SmartMedia Standard); and one ECC calculated over

512 bytes.

The ECC can correct any one-bit error or detect any two-bit error.

3.15.1 ECC Implementation

The two ECC configurations are selected by the ECCM bit:

ECCM = 0

Two 3 byte ECCs, each calculated over a 256 byte block of data.

This configuration conforms to the SmartMedia Standard.

Write any value to ECCRESET, then pass data across the GPIF

or Slave FIFO interface. The ECC for the first 256 bytes of data

is calculated and stored in ECC1. The ECC for the next 256 bytes

is stored in ECC2. After the second ECC is calculated, the values

in the ECCx registers do not change until ECCRESET is written

again, even if more data is subsequently passed across the

interface.

ECCM = 1

One 3 byte ECC calculated over a 512 byte block of data.

Write any value to ECCRESET then pass data across the GPIF

or Slave FIFO interface. The ECC for the first 512 bytes of data

is calculated and stored in ECC1; ECC2 is unused. After the

ECC is calculated, the values in ECC1 do not change even if

more data is subsequently passed across the interface, till

ECCRESET is written again.

3.16 USB Uploads and Downloads

The core has the ability to directly edit the data contents of the

internal 16 KByte RAM and of the internal 512 byte scratch pad

RAM via a vendor specific command. This capability is normally

used when soft downloading user code and is available only to

and from internal RAM, only when the 8051 is held in reset. The

available RAM spaces are 16 KBytes from 0x0000–0x3FFF

(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad

data RAM).

[8]

3.17 Autopointer Access

FX2LP provides two identical autopointers. They are similar to

the internal 8051 data pointers but with an additional feature:

they can optionally increment after every memory access. This

capability is available to and from both internal and external

RAM. The autopointers are available in external FX2LP registers

under control of a mode bit (AUTOPTRSET-UP.0). Using the

external FX2LP autopointer access (at 0xE67B – 0xE67C)

enables the autopointer to access all internal and external RAM

to the part.

Also, the autopointers can point to any FX2LP register or

endpoint buffer space. When autopointer access to external

memory is enabled, location 0xE67B and 0xE67C in XDATA and

code space cannot be used.

Notes

7. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

8. After the data has been downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.

[+] Feedback

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *M Page 13 of 62

3.18 I

C Controller

FX2LP has one I

C port that is driven by two internal controllers,

one that automatically operates at boot time to load VID/PID/DID

and configuration information, and another that the 8051 uses

when running to control external I

C devices. The I

C port

operates in master mode only.

3.18.1 I

C Port Pins

The I

C pins SCL and SDA must have external 2.2 kΩ pull up

resistors even if no EEPROM is connected to the FX2LP.

External EEPROM device address pins must be configured

properly. See Table 8 for configuring the device address pins.

3.18.2 I

C Interface Boot Load Access

At power on reset the I

C interface boot loader loads the

VID/PID/DID configuration bytes and up to 16 KBytes of

program/data. The available RAM spaces are 16 KBytes from

0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051

is in reset. I

C interface boot loads only occur after power on

reset.

3.18.3 I

C Interface General-Purpose Access

The 8051 can control peripherals connected to the I

C bus using

the I

CTL and I2DAT registers. FX2LP provides I

C master

control only, it is never an I

C slave.

3.19 Compatible with Previous Generation

EZ-USB FX2

The EZ-USB FX2LP is form, fit and with minor exceptions

functionally compatible with its predecessor, the EZ-USB FX2.

This makes for an easy transition for designers wanting to

upgrade their systems from the FX2 to the FX2LP. The pinout

and package selection are identical and a vast majority of

firmware previously developed for the FX2 functions in the

FX2LP.

For designers migrating from the FX2 to the FX2LP a change in

the bill of material and review of the memory allocation (due to

increased internal memory) is required. For more information

about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the

application note titled Migrating from EZ-USB FX2 to EZ-USB

FX2LP available in the Cypress web site.

Table 8. Strap Boot EEPROM Address Lines to These Values

Bytes Example EEPROM A2 A1 A0

16 24LC00

[9]

N/A N/A N/A

128 24LC01 0 0 0

256 24LC02 0 0 0

4K 24LC32 0 0 1

8K 24LC64 0 0 1

16K 24LC128 0 0 1

Table 9. Part Number Conversion Table

EZ-USB FX2

Part Number

EZ-USB FX2LP

Part Number

Package Description

CY7C68013-56PVC CY7C68013A-56PVXC or CY7C68014A-56PVXC 56-pin SSOP

CY7C68013-56PVCT CY7C68013A-56PVXCT or CY7C68014A-56PVXCT 56-pin SSOP – Tape and Reel

CY7C68013-56LFC CY7C68013A-56LFXC or CY7C68014A-56LFXC 56-pin QFN

CY7C68013-100AC CY7C68013A-100AXC or CY7C68014A-100AXC 100-pin TQFP

CY7C68013-128AC CY7C68013A-128AXC or CY7C68014A-128AXC 128-pin TQFP

Note

9. This EEPROM does not have address pins.

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