Freescale MPC5604B/C 微控制器参考手册部分汉化
3星 · 超过75%的资源 需积分: 25 58 浏览量
更新于2024-07-26
收藏 4.74MB PDF 举报 "MPC5602B部分汉化资料，包括了Freescale Semiconductor的MPC5604B/C Reference Manual的Rev.8.1版本和Reference Manual Addendum的Rev.1版本，主要涉及微控制器的参考资料。"
本文档提及的MPC5602B是一款由Freescale Semiconductor（现已被NXP半导体收购）生产的微控制器，它是MPC5604B/C系列的一部分。这个系列的微控制器通常用于需要高性能、低功耗和复杂控制功能的应用中，如汽车电子、工业自动化等领域。
MPC5604B/C Reference Manual是该微控制器的详细技术文档，包含了关于微控制器的架构、功能、寄存器描述、外设接口、编程模型以及应用示例等全面信息。Rev.8.1是手册的某个修订版本，通常随着产品的更新或发现错误后进行修正。而MPC5604B/C Reference Manual Addendum则是对原手册的补充，列出了在Rev.8.1基础上的修正和更新，以帮助用户获取最新的技术信息。
文档中提到的Rev.8.2的Addendum可能是对Rev.8.1的进一步修订，包含了更多的错误修复或新功能的介绍。Revision History章节会列出每个修订版本的变更内容，这对于开发者跟踪微控制器的改进和解决潜在问题至关重要。
由于原始资料是英文版，部分已由用户进行了汉化，但大部分内容仍为英文。对于希望使用这款微控制器的开发者来说，完全汉化文档的完成将极大地提高阅读和理解的效率，尤其是在没有专业英语背景的情况下。
MPC5602B的相关资料是理解并有效利用这款微控制器的关键，无论是硬件设计、固件开发还是系统集成，都需要参考这些详细的手册和修订记录。因此，这份汉化资料对于中国开发者社区的贡献是巨大的，它降低了技术学习和应用的门槛。同时，用户提供的持续更新和翻译也体现了开源和协作的精神，有助于技术信息的传播和共享。
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 11
22.1.2 FlexCAN module features ............................................................................................424
22.1.3 Modes of operation .......................................................................................................425
22.2 External signal description ............................................................................................................425
22.2.1 Overview ......................................................................................................................425
22.2.2 Signal descriptions ........................................................................................................426
22.3 Memory map and register description ...........................................................................................426
22.3.1 FlexCAN memory mapping .........................................................................................426
22.3.2 Message buffer structure ..............................................................................................428
22.3.3 Rx FIFO structure .........................................................................................................431
22.3.4 Register description ......................................................................................................433
22.4 Functional description ...................................................................................................................451
22.4.1 Overview ......................................................................................................................451
22.4.2 Local priority transmission ...........................................................................................452
22.4.3 Transmit process ...........................................................................................................452
22.4.4 Arbitration process .......................................................................................................453
22.4.5 Receive process ............................................................................................................454
22.4.6 Matching process ..........................................................................................................455
22.4.7 Data coherence .............................................................................................................456
22.4.8 Rx FIFO ........................................................................................................................459
22.4.9 CAN protocol related features ......................................................................................460
22.4.10 Modes of operation details ...........................................................................................464
22.4.11 Interrupts .......................................................................................................................465
22.4.12 Bus interface .................................................................................................................465
22.5 Initialization/Application information ...........................................................................................466
22.5.1 FlexCAN initialization sequence ..................................................................................466
22.5.2 FlexCAN addressing and SRAM size configurations ..................................................467
Chapter 23
Deserial Serial Peripheral Interface (DSPI)
23.1 Introduction ...................................................................................................................................469
23.2 Features .........................................................................................................................................470
23.3 Modes of operation ........................................................................................................................471
23.3.1 Master mode .................................................................................................................471
23.3.2 Slave mode ...................................................................................................................471
23.3.3 Module Disable mode ...................................................................................................471
23.3.4 Debug mode ..................................................................................................................472
23.4 External signal description ............................................................................................................472
23.4.1 Signal overview ............................................................................................................472
23.4.2 Signal names and descriptions ......................................................................................472
23.5 Memory map and register description ...........................................................................................474
23.5.1 Memory map ................................................................................................................474
23.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................475
23.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................478
23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................478
23.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................486
剩余928页未读，继续阅读
993 浏览量
161 浏览量
122 浏览量
2024-10-28 上传
2024-10-28 上传
2024-10-28 上传
242 浏览量
modalism
- 粉丝: 0
- 资源: 2
我的内容管理
展开
