超低功耗A7139无线通信芯片V2.1规格

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A7139是一款专为超低功耗无线通信设计的芯片，其工作频率覆盖了1GHz以下范围，例如常见的433MHz频段。该芯片主要作为FSK (Frequency Shift Keying) 和 GFSK (Gaussian Frequency Shift Keying) 传输器，适用于Sub1GHz频谱的通信系统。A7139 Datasheet V2.1提供了详细的规格和功能更新历史，自2012年9月的初步版本以来，经过多次修订和完善。早期版本（0.1）在2012年发布，主要关注文档标题、通用描述以及部分设置建议的更新。随着后续的版本迭代，芯片的功能逐渐增强。例如，0.4版本在2013年4月加入了宽带唤醒（WOR）预览和载波功能，增加了新的 preamble检测类型，以及配备了16K和无限长度FIFO（First In First Out）功能，以及自动IF（Intermediate Frequency）和自动重发/确认功能，提升了通信的灵活性和可靠性。在硬件特性方面，1.0版本优化了灵敏度数据，确保了在复杂环境中的有效通信。1.1版本删除了带内载波检测的描述，并更新了MD7139-A50应用电路。1.2版本对AGC控制II（Automatic Gain Control）和RGVA值进行了修改，提高了信号处理性能。在1.3版本中，修正了一个关于芯片内置ID位数的错误，将其从32位改为了64位，增强了芯片的身份识别能力。干扰数据在1.4版本中得到了更新，确保了在多径干扰环境下的稳定通信。1.5版本增加了安全警示声明，强调了正确使用芯片的重要性和潜在的安全注意事项。1.6版本修订了第8章的格式，1.7版本则调整了WOR同步的相关设置。总体来说，A7139 Datasheet V2.1提供了详尽的技术规格，涵盖了芯片的工作原理、频率兼容性、功能特性、性能参数以及使用和维护建议，这对于开发基于A7139的无线通信设备和系统的设计者和工程师来说，是不可或缺的参考资料。随着无线通信技术的发展，A7139芯片也在不断适应市场需求，持续进行优化和升级。

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A7139

FSK/GFSK Sub 1GHz Transceiver

Oct., 2016, Version 2.1 AMICCOM Electronics Corporation

Pease refer to Chapter 13 for detail.

9.2.3 PLL II (Address: 02h)

Address/Name

R/W

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

02h

PLL II

W FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0

Reset

FP[15:0]: LO Frequency Fractional Part setting.

(unit: Hz)

where , the base frequency of VCO

where , the comparison frequency of RF_PLL.

A7139’s RF frequency is implemented by an offset scheme regarding to the below formula.

The wanted RF frequency is equal to VCO frequency, F

= F

VCO

= F

LO_BASE

+ F

OFFSET.

where , the offset frequency of VCO is set by FPA [15:0] (09h, page 2)

Please refer to Chapter 13 for details.

9.2.4 PLL III (Address: 03h)

Address/Name

R/W

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

03h

PLL III

AFC

MC14

MC13

MC12

MC11

MC10

MC9

MC8

MC7

MC6

MC5

MC4

MC3

MC2

MC1

MC0

AFC

MC14

MC13

MC12

MC11

MC10

MC9

MC8

MC7

MC6

MC5

MC4

MC3

MC2

MC1

MC0

Reset

AFC: Auto Frequency Compensation selection.

[0]: manual

[1]: auto

MC[14:0]: PLL Fractional Part Compensation value.

[Write]：Manual setting to LO fractional part compensation value when AFC = [0].

[Read]：Frequency offset value when AFC = [1].

9.2.5 PLL IV (Address: 04h)

Address/Name

R/W

Bit15 Bit14 Bit13 Bit12

Bit11

Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

04h

PLL IV

W TXDBG

EDIVS

CKX2

MD1 PDL2

PDL1 PDL0

MD0

ADCR

VCl CPS

ISDIV SDPW1

SDPW0

NSDO

EDI

Reset

TXDBG: TX Debug mode. TXDBG shall be [0].

[0]: Disable

[1]: Enable

EDIVS: Synthesizer Selection. EDIVS shall be [0].

[0]: Fractional-N PLL

[1]: Reserved

MD1: RF Band select.

[0]: Low band (310MHz ~ 510MHz)

[1]: High band (860MHz ~ 930MHz)

CKX2: Reserved. CKX2 shall be [0].

MD0: LO Buffer current select.

[0]: Low current

[1]: High current

PDL[2:0]: PLL Settling Delay Time setting.

PDL [2:0]

PLL Delay Timer

Note

)

]0:15[

]0:8[(

LO_BASE

IPff

PFD

+⋅=

LO_BASE

)1]0:3[(

PFD

+÷= RFCff

Xtal

OFFSET

)

2]0:15.[

(

OFFSET

⋅

⋅=

FPA

PFD

AMICCOM CONFIDENTIAL

A7139

FSK/GFSK Sub 1GHz Transceiver

Oct., 2016, Version 2.1 AMICCOM Electronics Corporation

000

20 us

001

40 us

010

60 us

011

80 us

Recommend

100

100 us

101

120 us

110

140 us

111

160 us

ADCR: Reserved. ADCR should be= [0].

VCI: VCO current calibration test bit. Reserved. VCl shall be [0].

CPS: Charge Pump tri-state setting. Recommend CPS = [1].

[0]: Tri-state.

[1]: Normal operation.

ISDIV: Divider current test bit. Recommend ISDIV = [0].

[0]: low current.

[1]: high current.

SDPW[1:0]: Pulse Width of sigma-delta modulator. SDPW shall be [00].

NSDO: Mash sigma delta order setting. Recommend NSDO = [0].

[0]: order 2. [1]: order 3.

EDI: Dither Noise setting. Recommend EDI = [0].

[0]: Disable. [1]: Enable.

9.2.6 PLL V (Address: 05h)

Address/Name

R/W

Bit15 Bit14 Bit13

Bit12 Bit11 Bit10

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h

PLL V

W VICMP

IA14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0

Reset

VICMP: Reserved. VICMP shall be [0].

IA[14:0]: Reserved. IA shall be [0x0000].

9.2.7 PLL VI (Address: 06h)

Address/Name

R/W

Bit15 Bit14 Bit13

Bit12 Bit11 Bit10

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

06h

PLL VI

W RFC3 RFC2

RFC1

RFC0

RIC11

RIC10

RIC9 RIC8 RIC7 RIC6 RIC5 RIC4 RIC3

RIC2 RIC1 RIC0

Reset

RFC[3:0]: R-Counter for Fractional-N PLL

RFC is used to divide crystal frequency for the comparison frequency of the Franc-N PLL by

PFD

= Fxtal / (RFC[3:0]+1)

RIC[11:0]: Reserved. RIC shall be [0x000]

9.2.8 Crystal (Address: 07h)

Address/Name

R/W

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6

Bit 5

Bit 4

Bit 3 Bit 2 Bit 1

Bit

07h

Crystal

PGAS3

PGAS2

PGAS1

PGAS0

CRCDNP

CRCINV

PGBS2

PGBS1

PGBS0

RBS - XCC

XCP1

XCP0

CGS

Reset

PGAS[3:0]: Page selector for the 08h register.

CRCDNP: CRC Mode Select.

[0]: CRC-CCITT (X

+ X

+ 1).

[1]: CRC-DNP (X

+ X

+ 1).

CRCINV: CRC Inverted Select.

[0]: disable. [1]: enable

AMICCOM CONFIDENTIAL

A7139

FSK/GFSK Sub 1GHz Transceiver

Oct., 2016, Version 2.1 AMICCOM Electronics Corporation

PGBS[2:0]: Page selector for the 09h register.

RBS: REGA bandgap setting.

XCC: Crystal Current setting.

[0]: Low current. [1]: High current.

XCP[1:0]: Crystal Regulating Couple setting. Recommend XCP =[00].

CGS: Clock Generation Selection.

[0]: Disable, F

MSCK

= Xtal freq.

[1]: Enable, F

MSCK

= CLK Generator. Please refer to chapter 12 for details.

XS: Crystal Oscillator Selection. Recommend XS = [1].

[0]: Disable [1]: Enable

9.2.9 TX I (Address: 08h) Page 0

Address/Name

R/W

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h

TX I

RC_DL

TME GS FDP2 FDP1 FDP0 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0

Reset

RC_DLY[2:0]: RSSI calibration RL Delay setting. Recommend RC_DLY= [000]

[000]: 100us. [001]: 300us. [010]: 500us. [011]: 700us.

[100]: 900us. [101]: 1.1ms. [110]: 1.3ms. [111]: 1.5ms.

TME: TX Modulation Enable.

[0]: Disable.

[1]: Enable.

GS: Gaussian Filter Selection.

[0]: Disable.

[1]: Enable.

FDP[2:0]: Frequency Deviation Exponential Coefficient setting.

FD[7:0]: TX Frequency Deviation setting.

For both Gaussian filter is enabled (GS =1) or disabled（GS = 0）：

(unit: Hz)

where , is the comparison frequency of RF_PLL.

Note2: please refer to Chapter 13 for details.

9.2.9.1 WOR I (Address: 08h) Page1

Address/Name

R/W

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h

TX I

WOR

_AC5

WOR

_AC4

WOR

_AC3

WOR

_AC2

WOR

_AC1

WOR

_AC0

WOR

_SL9

WOR

_SL8

WOR

_SL7

WOR

_SL6

WOR

_SL5

WOR

_SL4

WOR

_SL3

WOR

_SL2

WOR

_SL1

WOR

_SL0

VBD

Reset

WOR_AC [5:0]: 6-bits WOR Active Period.

WOR Active Period = (WOR_AC[5:0]+1) x (1/4096), (244us ~ 15.6ms).

WOR_SL [9:0]: 10-bits WOR Sleep Period.

WOR Sleep Period = (WOR_SL[9:0]+1) x (32/4096), (7.8ms ~ 7.99s).

]0:2[

]0:7[2

FDP

DPdev

FDff ⋅⋅⋅=

)1]0:3[(

PFD

+÷= RFCff

Xtal

AMICCOM CONFIDENTIAL

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