高性能架构的编译器优化技术

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"本书章节涉及了现代高性能架构中编译器面临的挑战，涵盖了从流水线技术、向量指令、超标量和VLIW处理器、处理器并行性、内存层次结构到高级编译技术等多个重要主题，旨在通过优化编译器来提升程序运行速度和效率。" 在现代计算机体系结构中，编译器扮演着至关重要的角色，它们不仅要将高级语言转化为机器可执行的代码，还要负责优化这些代码以适应特定硬件架构，从而提高程序的运行效率。本书的第一章“现代体系结构的优化编译器”深入探讨了这一主题。 1.1 概览与目标这一部分阐述了编译器优化的基本理念和目标，即在保证正确性的前提下，最大限度地挖掘硬件性能，提升程序执行速度。 1.2 流水线技术书中详细介绍了流水线执行的概念，包括指令单元的流水线（1.2.1）和执行单元的流水线（1.2.2）。流水线技术通过重叠处理不同阶段的指令，提高了处理器的吞吐量。同时，还讨论了并行功能单元（1.2.3）如何进一步增强这种并行处理能力，并且针对标量流水线的编译策略（1.2.4）进行了分析。 1.3 向量指令向量指令（1.3）是提高性能的另一种手段，通过同时处理多个数据元素，特别适合于大规模数据运算。书中概述了向量硬件的基本工作原理（1.3.1），并探讨了如何为向量管道进行编译优化（1.3.2）。 1.4 超标量和VLIW处理器这部分（1.4）介绍了多发指令单元（1.4.1）和多发处理器的编译技术（1.4.2），这些技术允许处理器在同一时钟周期内执行多个指令，以实现更高程度的并行计算。 1.5 处理器并行性处理器并行性（1.5）关注异步并行性，其中编译器必须处理不同指令流的同步问题。在1.5.1中，讲述了如何为异步并行性进行编译优化。 1.6 内存层次结构内存层次结构（1.6）的优化对性能影响显著。1.6.1部分讲解了如何针对内存层次结构进行编译，以减少访问延迟并提高缓存利用率。 1.7 实例研究：矩阵乘法通过矩阵乘法的案例（1.7），作者展示了优化技术如何应用于实际问题，以改善大规模计算任务的性能。 1.8 高级编译技术 1.8.1部分讨论了依赖性分析，这是编译器优化的基础，而1.8.2部分则探讨了各种变换技术，如循环展开、指令调度等，用于消除依赖并增强并行性。 1.9 章节总结这一部分回顾了本章的主要内容，帮助读者巩固理解。 1.10 案例研究和历史评论这部分提供了更多的实践应用示例，以及对编译器优化领域历史发展的评论。 1.11 练习通过练习题，读者可以检验和巩固所学知识。 1.12 参考文献列举了相关领域的参考书籍和论文，供进一步学习。第二章“依赖性：理论与实践”（2.1至2.2.2）则进一步深入到依赖性的概念，包括负载-存储分类和循环中的依赖性分析，这些都是优化编译器时必须考虑的关键因素。这些章节详细阐述了编译器优化的各种策略和技术，对于理解现代高性能计算机体系结构以及如何利用编译器提升其效能具有重要价值。

Compiler Challenges for High-Performance Architectures

18 ADVANCED COMPILING FOR HIGH PERFORMANCE

by Moore’s law. However, technology by itself has not been enough.

Figure 1.1 plots the peak performance of the fastest supercomputer by

year from 1950 to 2000. The regression ﬁt, which follows Moore’s law

quite well, indicates that supercomputer performance has increased by

two orders of magnitude every decade. However, the four outlined

regions show that differences in computer architecture—from scalar

through superscalar and vector to parallel—have been necessary to keep

performance on track. Clearly parallelism of one form or another is

essential to supercomputing.

FIGURE 1.1 Performance of the fastest supercomputers over 50 years.

But parallelism is not just for supercomputers anymore. Even though

today’s uniprocessors are faster than they have ever been, the growth of

image processing applications and multimedia on the desktop has created

an enormous thirst for more processing power. To keep up with this

demand, uniprocessor designs have included many features employing

parallelism, such as multiple functional units, multiple-issue instruction

processing, and attached vector units. Still, all the power added by these

strategies cannot satisfy the computational requirements for computation

servers, which generally employ modest numbers (4 to 32) of processors.

Clearly, parallelism has become a signiﬁcant factor in the marketplace.

EDSAC 1

UNIVAC 1

IBM 7090

CDC 6600

IBM 360/195CDC 7600

Cray 1

Cray X-MP

Cray 2

TMC CM-2

TMC CM-5

Cray T3D

ASCI Red

1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000

1 KFlop/s

1 MFlop/s

1 GFlop/s

1 TFlop/s

Scalar

Superscalar

Vector

Parallel

Overview and Goals

Chapter Draft of February 8, 2001 19

Parallelism is not the only distinguishing factor in the design of high-per-

formance computers. Because of the rapidly growing processor speed

and the relatively slow pace of improvement of memory technology, most

of today’s processors have two or three levels of cache memory. These

caches are designed to hide the long latencies inherent in the mismatch

between processor speed and memory access time. They also improve

effective memory bandwidth for data that is reused from cache.

Advances in computing power have not come without problems, how-

ever. As the computing systems have grown more complex to keep apace

of Moore’s Law, they have become ever more difﬁcult to program. Most

high-end application developers are painfully aware of the tricks needed

to explicitly manage memory hierarchies and communication in today’s

scalable parallel systems. In an effort to squeeze more performance out of

individual processors, programmers have even learned how to transform

their codes by hand to improve instruction scheduling on multiple-issue

uniprocessors.

It is our view that most of these hand transformations for high perfor-

mance computers should really be performed by the compiler, libraries,

and run-time system. The compiler must play a special role because of its

traditional responsibility for translating programs from a language suit-

able for use by human application developers to the native language of

the target machine. It is tempting to believe that compiler’s responsibility

ends with the production of a correct machine-language translation of the

source program. By itself, however, this is not enough. The compiler

must produce a suitably efﬁcient program as well. If it fails to do so,

application developers may well abandon attempts to use the language.

The importance of efﬁciency in compiled code is not a recent observa-

tion—it has been implicit in the development of every successful com-

puter language beginning with the ﬁrst version of Fortran

.In the words of

John Backus, reﬂecting in 1978 on the Fortran

I effort [7]:

It was our belief that if Fortran, during its ﬁrst months, were to translate

any reasonable “scientiﬁc” source program into an object program only

half as fast as its hand-coded counterpart, then acceptance of our system

would be in serious danger. ...To this day I believe that our emphasis on

object program efﬁciency rather than on language design was basically

correct. I believe that had we failed to produce efﬁcient programs, the

widespread use of languages like Fortran would have been seriously

delayed.

In fact, I believe that we are in a similar, but unrecognized, situation

today: in spite of all the fuss that has been made over myriad language

Compiler Challenges for High-Performance Architectures

20 ADVANCED COMPILING FOR HIGH PERFORMANCE

details, current conventional languages are still very weak program-

ming aids, and far more powerful languages would be in use today if

anyone had found a way to make them run with adequate efﬁciency.

These words are as true today as they were four decades ago, when For-

tran was ﬁrst developed. In fact, compiler technology has become even

more important as machines have become more complex. The success of

each innovation in computer architecture has been contingent on the abil-

ity of compiler technology to provide efﬁcient language implementations

on that architecture—in other words, the trend in modern machine archi-

tecture has been to shift the burden of achieving high performance from

the hardware to the software. In this task, compiler technology has been

only partially successful. Excellent techniques have been developed for

vectorization, instruction scheduling, and management of multilevel

memory hierarchies. Automatic parallelization, on the other hand, has

been successful only for shared-memory parallel systems with a few pro-

cessors—compiler parallelization for scalable machines remains an

unsolved problem to this day.

Fortunately, there is substantive commonality in the underlying analysis

structure needed to compile for the diverse collection of high perfor-

mance computer architectures available today. Most critical compilation

tasks can be handled by transformations that reorder the instances of

statements in the original program. To perform these transformations in a

way that preserves the original meaning of the program, modern compil-

ers employ the concept of dependence, which indicates when it is unsafe

to interchange the order of two statement instances. Dependence has

turned out to be an amazingly durable and broadly applicable concept. In

point of fact, this book might well be titled “Dependence-based compila-

tion: theory and practice,” because dependence is the unifying theme for

the entire volume.

It is the principal goal of this book to provide an introduction to depen-

dence and the many transformation strategies that it supports. These com-

piler technologies have been developed over the past two decades to deal

with machine complexity at the high end. Our aim is to provide a useful

resource for the student of advanced compilation and the practicing com-

piler developer alike. The remainder of this chapter consists of a brief

introduction to high-performance computer architectures followed in

each case by a discussion of the compiler strategies needed to deal with

them. The trade-offs among these strategies are illustrated by an extended

example in which the same program is shown optimized for different

Compiler Challenges for High-Performance Architectures

22 ADVANCED COMPILING FOR HIGH PERFORMANCE

modern RISC machines, including the MIPS architecture found in

machines manufactured by SGI.

On a modern RISC machine, typical instructions take on three forms:

• Register-to-register ALU operations. These include all arithmetic

operations such as integer and ﬂoating point addition, subtraction and

so on.

• Memory operations. These instructions require a memory access.

Load from memory into registers and store into memory are both of

this type.

• Branch instructions. These instructions change the location in mem-

ory from which the next instruction is to be executed, depending on

the value of a condition. If the condition is true, the program counter is

incremented by the immediate value in the instruction, otherwise the

PC is left pointing to the next instruction in memory. If

The DLX pipeline is designed to handle all three kinds of instructions.

The pipeline includes the following stages:

1. instruction fetch (IF),

2. instruction decode (ID)

3. execute (EX) and

4. memory access (MEM) and

5. write back (WB).

Instruction fetch and decode are self explanatory. For the purposes of

execution, the EX and MEM phases are grouped. If the instruction is a

ical unit (ALU), the instruction is completed in the EX phase. If it is a

memory access, address calculation is performed in the EX phase and the

memory access actually takes place in the MEM phase. Note that if the

required memory location is not in cache, a miss occurs and the instruc-

tion will stall until the required block is brought into cache. If the instruc-

tion is a branch, the speciﬁed register is compared to zero in the

execution phase and the PC is set to the correct value in the MEM phase.

The WB phase is used to write data back to registers; it is not used in a

branch instruction.

If each pipeline stage uses different resources, the different stages of suc-

cessive instructions can be overlapped, as in the schedule of execution

shown in Figure 1.2, which is able to issue an instruction on every

machine cycle. In other words, the average number of cycles per instruc-

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