JEDEC 2023 GDDR6 SGRAM 标准详解

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"JEDEC JESD 250D-2023 Graphics Double Data Rate (GDDR6) SGRAM Standard.pdf" 这篇文档是JEDEC固态技术协会于2023年5月发布的关于GDDR6显存标准的详细规范，即JESD 250D标准。GDDR6是一种高性能的图形双倍数据速率同步图形随机存取内存（SGRAM），用于提升图形处理单元（GPU）的数据传输速度和性能。这个标准是对2021年2月版本JESD 250C的修订。 GDDR6的主要特点和改进包括： 1. **更高的数据速率**：相比上一代GDDR5，GDDR6提供更高的数据传输速率，可以达到16 Gbps或更高，显著提升了GPU的带宽，支持更复杂、更大数据需求的应用，如4K及以上的高分辨率游戏、专业图形渲染和人工智能计算。 2. **双倍数据速率**：GDDR6的工作原理是在每个时钟周期的上升沿和下降沿都传输数据，因此数据传输速率是单边沿传输的两倍，从而实现比GDDR5更高的带宽。 3. **更有效的功耗管理**：尽管速度提升，但GDDR6通过优化的电路设计和制造工艺实现了相对较低的功率消耗，使得高性能与能效得以平衡。 4. **增强的错误校验**：GDDR6引入了更先进的错误检测和校正机制，如CRC（循环冗余校验），以提高数据传输的可靠性和稳定性。 5. **扩展的I/O接口**：GDDR6的接口通常具有更宽的数据通道，例如32位或更宽，以适应高带宽需求，同时保持与前代兼容的引脚定义。 6. **更精细的电压控制**：GDDR6允许更精细的电压控制，以确保在不同工作条件下的稳定运行。 7. **兼容性与互操作性**：JEDEC标准旨在促进不同制造商之间的产品互换性，确保所有符合该标准的GDDR6内存模块都能无缝工作，不论是在国内还是国际市场。 JEDEC标准的制定遵循严格的程序，经过JEDEC董事会和法律顾问的审查批准，目的是消除制造商和消费者之间的误解，促进产品间的互换性，并协助购买者快速准确地选择合适的产品。同时，JEDEC并不负责解决标准可能涉及的专利问题，不承担任何专利持有者的责任，也不对任何一方产生义务。这意味着采用该标准的公司需要自行处理可能存在的专利权问题。

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JEDEC Standard No. 250D

Page 4

2.3 Definition of Signal State Terminology

GDDR6 SGRAM will be operated in both ODT Enable (terminated) and ODT Disable (unterminated) modes. For

highest data rates it is recommended to operate in the ODT Enable mode. ODT Disable mode is designed to reduce

power and may operate at reduced data rates. There exist situations where ODT Enable mode can not be guaranteed

for a short period of time, i.e., during power up.

Following are four terminologies defined for the state of a device (GDDR6 SGRAM or controller) signal during

operation. The state of the bus will be determined by the combination of the device signal connected to the bus in the

system. For example, in GDDR6 it is possible for the SGRAM pin to be tristated while the controller signal is HIGH

or ODT. In both cases the bus would be HIGH if the ODT is enabled. For details on the device’s signals and their

function see Sections 9.1 and 9.5.

Device pin signal level:

• HIGH: A device signal is driving the Logic “1” state.

• LOW: A device signal is driving the Logic “0” state.

• Hi-Z: A device signal is tristate.

• ODT: A device signal terminates with ODT setting, which could be terminating or tristate depending on Mode

Bus signal level:

• HIGH: One device on bus is HIGH and all other devices on bus are either ODT or Hi-Z. The voltage level on the

bus would be nominally V

DDQ

• LOW: One device on bus is Low and all other devices on bus are either ODT or Hi-Z. The voltage level on the

bus would be nominally VOL(DC) if ODT was enabled, or V

if Hi-Z.

• Hi-Z: All devices on bus are Hi-Z. The voltage level on bus is undefined as the bus is floating.

• ODT: At least one device on bus is ODT and all others are Hi-Z. The voltage level on the bus would be

nominally V

DDQ

2.4 Definition of Clocking Terminology

• Data refers to the signal being clocked (e.g., DQ by WCK and CA by CK

• Half rate: clock is running at half of the data rate (e.g., WCK 4 GHz and DQ at 8 Gbps, or CK 1 GHz and CA at

2 Gbps)

• Quarter rate: clock is running at a quarter of the data rate (e.g., WCK 2 GHz and DQ at 8 Gbps)

• Eighth rate: clock is running at one eighth of the data rate (e.g., WCK internal 1 GHz and DQ at 8 Gbps)

• DDR (Double Data Rate): complement to half rate, referring to data relative to clock

• QDR (Quad Data Rate): complement to quarter rate, referring to data relative to clock

• ODR (Octa Data Rate): complement to eighth rate, referring to data relative to clock

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JEDEC

JEDEC Standard No. 250D

Page 5

2.5 Clocking

The GDDR6 SGRAM supports two operating modes for WCK frequency which differ in the DQ/DBI_n pin to WCK

clock frequency ratio. The GDDR6 SGRAM supports DDR and QDR operating modes for WCK frequency which

differ in the DQ/DBI_n to WCK clock frequency ratio.

Figure 1 illustrates the difference between a DDR WCK and a QDR WCK. Figure 61 illustrates a WRITE command

with a DDR WCK clock while Figure 62 illustrates a WRITE command with a QDR WCK clock. Figure 76

illustrates a READ command with DDR WCK clocking and Figure 77 illustrates a READ command with QDR

WCK clocking. Other figures in the specification are shown only with the DDR WCK for simplicity unless otherwise

noted.

GDDR6 SGRAM also supports 2 granularities for the WCK data clock in the device. GDDR6 SGRAM devices can

be designed with either a WCK/byte or a WCK/word. The ball-out has provisions for a WCK/byte but also supports

WCK/word with the unused WCK balls as NC; the host must turn the unused WCK off.

The DRAM info bits for WCK Granularity, WCK Frequency and Internal WCK can be read by the host during the

initialization process to determine the WCK architecture for the device and for devices that support multiple

frequencies, MR10 OP9 allows for the mode to be set. For the frequencies for each mode see Table 73.

In both WCK QDR and DDR modes the GDDR6 device operates from a differential clock CK_t and CK_c.

Command and Address (CA) are registered at every rising and falling CK edge. For both WCK DDR and QDR ratio

the GDDR6 device can support either a full data rate EDC or a half data rate EDC. See EDC section for more details.

A rising CK (or WCK) edge is defined as the crossing of the positive edge of CK_t (or WCK_t) and the negative edge

of CK_c (or WCK_c). A falling CK (or WCK) edge is defined as the crossing of the negative edge of CK_t (or

WCK_t) and the positive edge of CK_c (or WCK_c).

Table 1 — Example Clock and Interface Signal Frequency Relationship

PIN DDR WCK QDR WCK UNIT

CK_t, CK_c 1.5 1.5 GHz

CA 3.0 3.0 Gbps/pin

WCK_t, WCK_c 6.0 3.0 GHz

DQ, DBI_n 12.0 12.0 Gbps/pin

EDC 6.0 12.0 6.0 12.0 Gbps/pin

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JEDEC

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