DS_HYDRA3D– REV1.1 –2020-06-04 17
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The Pixel Array. It is composed of 832 x 600 active pixels plus 128 x 600 pixels covered with
metals (OB columns) for measuring horizontal fixed-pattern noise. Additional dummy rows and
columns are included.
The Readout Channel. In charge of conditioning and digitizing the analog data from the pixel
array. The architecture implemented is a column-parallel approach. In particular, it encloses
three analog-to-digital converters per column, enabling the conversion of the 3 floating
diffusion of the currently read pixel simultaneously.
The serialization block (SPS). The SPS is a digital block that serializes the digital pixel data
towards the Digital Image Processor (DIP).
Digital Image Processor (DIP). The digital signal processor in Hydra3D is in charge of HFPN
correction and calculation of the CRC of the pixel data.
Control main (SCM). This block is in charge of controlling the complete signal path sub-blocks:
pixel array, readout, digital signal processing, and output stages. It implements the necessary
logic that contains the main control machines.
The Row-Control Block (SSH). The SSH is a digital block in charge of providing the rows of the
pixel array with the appropriate control signals in time. In this case, this block must be duplicated
on both sides of the pixel array in order to achieve the target timing for the control signals of the
pixel.
The row-control buffers (AnaCtrlRow). This analog block provides driving capability and
appropriate voltage levels to the digital signals delivered by the SSH to control the Pixel Array
operation.
Programming Interface (Global Programming block, GPR): This block includes the SPI and Design-
for-Test blocks. The SPI communication interface allows an external host to configure and control
the ASIC by writing/reading registers and memories.
Image Interface: The image data is transmitted through several LVDS ports. In this case 13 LVDS
data ports are included, plus 1 LVDS port containing the recovery clock and 1 LVDS synchronism
port.
Clock Generation Unit (CGU): This block generates the necessary clocks for sensor operation. It
contains a low-jitter low-power Phase Locked Loop (PLL).
The OTP Memory Block. This block embeds non-volatile memory cells.
Vddpix Block. This block distributes the supplies required by the pixel array operation.
Analog References. This block generates the internal analog references required by the sensor
operation. The references are generated from a high-accuracy bandgap.
Temperature Sensor. The temperature sensor consists of an integrated PNP transistor in
combination with low-cost external component (MAX6642) which allows an accuracy of up to
0.25ºC in the temperature measurement.