UDX710开发规格说明书概述

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UDX710 Device Specification_v1.0是由展锐（UNISOC）提供的一份详细的技术规格文档，该文档涵盖了处于开发阶段的UDX710芯片的信息。这份规格书是展锐通信技术有限公司的机密财产，包含了关于该芯片的重要设计细节、功能特性以及性能参数。首先，文档的标题表明了它主要关注的是UDX710的具体规格，这可能是一款用于移动通信设备或物联网应用的SoC（系统-on-a-chip）。展锐是一家专注于无线通信解决方案的公司，所以UDX710可能是他们针对5G、4G、LPWA（低功耗广域网）等无线标准开发的产品。在描述部分，我们了解到UDX710属于一个正在开发中的产品，这意味着它可能尚未正式发布，但展锐已经对其进行了深入研究并准备了详细的规格说明。这份文档可能包括以下关键内容： 1. **硬件架构**：文档会详述UDX710的处理器核心、内存、接口（如USB、PCIe）、无线通信模块（如基带、射频）、电源管理和散热方案等硬件组成部分。 2. **功能特性**：如支持的通信标准（如5G NR、LTE、NB-IoT）、多模支持、数据处理能力、多媒体处理单元、安全功能等。 3. **性能指标**：如处理器速度、功耗、带宽、时延、吞吐量等关键性能参数。 4. **软件兼容性**：可能包含操作系统兼容性、SDK（软件开发工具包）信息和驱动程序需求。 5. **安全性与隐私**：强调UNISOC对UNISOC Confidential Information的保护措施，以及关于版权和商标声明，表明他们尊重知识产权，并警告未经授权的复制和分发。 6. **免责声明**：说明文档提供的信息不构成任何保证，包括明示或暗示的质量、性能或适用性保证，用户需要自行评估其在特定应用中的适用性。作为一份技术规格文档，UDX710 Device Specification_v1.0对于开发人员、系统集成商和产品经理来说，是了解和设计基于UDX710芯片的设备时不可或缺的参考资料。阅读和理解这份文档可以帮助他们优化设计决策，确保产品的兼容性和性能满足市场需求。

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UDX710 Device Specification

V1.0 UNISOC Communications, Inc., Confidential and Proprietary 16 of 2899

This document contains information on a product under development.

UNISOC reserves the right to change or discontinue this product without notice.

5.12.7 Implementations .............................................................................................735

5.12.8 Future improvements .....................................................................................735

5.13 EIC .................................................................................................................................735

5.13.1 Overview ........................................................................................................735

5.13.2 Features .........................................................................................................735

5.13.2.1 EIC_DBNC ...................................................................................735

5.13.2.2 EIC_LATCH .................................................................................735

5.13.2.3 EIC_ASYNC .................................................................................736

5.13.2.4 EIC_SYNC ...................................................................................736

5.13.3 Signal Description ..........................................................................................736

5.13.4 Function Description ......................................................................................736

5.13.4.1 DBNC FSM ..................................................................................737

5.13.4.2 CPU trigger de_bounce circuit at regular intervals waveform .....738

5.13.5 Control Registers ...........................................................................................738

5.13.5.1 Memory map ................................................................................738

5.13.5.2 Register description .....................................................................738

5.13.5.3 Register Descriptions ...................................................................740

5.13.6 Application Notes ...........................................................................................761

5.13.6.1 Software control flow ....................................................................761

5.13.7 Programming Notes .......................................................................................764

5.13.8 Implementations .............................................................................................764

5.13.9 Future improvements .....................................................................................764

5.14 INTC ..............................................................................................................................764

5.14.1 Overview ........................................................................................................764

5.14.2 Features .........................................................................................................764

5.14.3 Signal Description ..........................................................................................765

5.14.4 Function Description ......................................................................................765

5.14.5 Control Registers ...........................................................................................767

5.14.5.1 Memory map ................................................................................767

5.14.5.2 Register Descriptions ...................................................................768

5.14.6 Application Notes ...........................................................................................776

5.14.7 Source Description .........................................................................................778

5.14.7.1 AON_INT_SOURCE ....................................................................778

5.14.7.2 AP_INTC0_SOURCE ..................................................................779

5.14.7.3 AP_INTC1_SOURCE ..................................................................780

5.14.7.4 AP_INTC2_SOURCE ..................................................................781

5.14.7.5 AP_INTC3_SOURCE ..................................................................782

5.14.7.6 AP_INTC4_SOURCE ..................................................................783

5.14.7.7 AP_INTC5_SOURCE ..................................................................785

5.14.7.8 PUB_CP_INTC_SOURCE ...........................................................786

5.14.7.9 WTL_CP_INTC_SOURCE ...........................................................787

5.14.7.10 TGDSP_INTC_SOURCE .............................................................788

5.14.7.11 LDSP_INTC_SOURCE ................................................................790

5.14.8 Application notes ............................................................................................791

5.14.9 Implementations .............................................................................................791

5.15 Thermal Controller .........................................................................................................791

5.15.1 Overview ........................................................................................................791

5.15.2 Features .........................................................................................................791

UDX710 Device Specification

V1.0 UNISOC Communications, Inc., Confidential and Proprietary 17 of 2899

This document contains information on a product under development.

UNISOC reserves the right to change or discontinue this product without notice.

5.15.3 Signal Description ..........................................................................................791

5.15.4 Function Description ......................................................................................792

5.15.4.1 Overall architecture ......................................................................792

5.15.4.2 THM work status ..........................................................................798

5.15.4.3 THM interrupt mode .....................................................................800

5.15.4.4 The temperature detect flow of THM ...........................................800

5.15.4.5 The figure4-5 synchronization OR-GATE flow .............................801

5.15.4.6 The case of sensor_det_peri_load < sensor_mon_cnt ................801

5.15.4.7 The case of temperature threshold is out of order .......................802

5.15.4.8 Working enable and reset of THM ...............................................802

5.15.4.9 FSM ..............................................................................................802

5.15.5 Control Registers ...........................................................................................807

5.15.5.1 Memory map ................................................................................807

5.15.5.2 Register Descriptions ...................................................................808

5.15.6 Application Notes ...........................................................................................822

5.15.7 Implementations .............................................................................................823

5.15.8 Future improvements .....................................................................................823

5.16 ADI .................................................................................................................................823

5.16.1 Overview ........................................................................................................823

5.16.2 Features .........................................................................................................824

5.16.3 Signal Description ..........................................................................................824

5.16.4 Function Description ......................................................................................825

5.16.4.1 ADI Master ...................................................................................825

5.16.4.2 ADI Master channel Configuration ...............................................826

5.16.4.3 ADI Slave .....................................................................................836

5.16.4.4 Adi clk path ...................................................................................838

5.16.5 Control Registers ...........................................................................................838

5.16.5.1 Memory map ................................................................................838

5.16.5.2 Register description .....................................................................838

5.16.5.3 Memory map ................................................................................838

5.16.5.4 ARM Register Descriptions ..........................................................842

5.16.6 Application Notes ...........................................................................................917

5.16.6.1 SDC constraint check ..................................................................917

5.16.6.2 Hardware channel mode program examples ...............................917

5.16.6.3 Hardware channel mode program examples (APB_WR_CMD,

APB_RD_CMD) .............................................................................................918

5.16.6.4 Programming Notes .....................................................................918

5.16.7 Implementations .............................................................................................918

5.16.8 Future improvements .....................................................................................918

5.17 GPIO ..............................................................................................................................919

5.17.1 Overview ........................................................................................................919

5.17.2 Features .........................................................................................................919

5.17.3 Signal Description ..........................................................................................919

5.17.4 Function Description ......................................................................................920

5.17.5 Control Registers (wrap up with 16-bit) .........................................................920

5.17.5.1 Memory map ................................................................................920

5.17.5.2 Register description .....................................................................920

5.17.6 Application notes ............................................................................................927

UDX710 Device Specification

V1.0 UNISOC Communications, Inc., Confidential and Proprietary 18 of 2899

This document contains information on a product under development.

UNISOC reserves the right to change or discontinue this product without notice.

5.17.7 Implementations .............................................................................................933

5.18 Efuse .............................................................................................................................933

5.18.1 Overview ........................................................................................................933

5.18.2 Features .........................................................................................................933

5.18.3 Signal Description ..........................................................................................933

5.18.4 Function Description ......................................................................................934

5.18.4.1 Block Diagram ..............................................................................934

5.18.4.2 Register File .................................................................................934

5.18.4.3 Efuse_Core ..................................................................................936

5.18.4.4 Power_on_read ............................................................................936

5.18.4.5 CLOCK and RST..........................................................................936

5.18.5 Control registers .............................................................................................937

5.18.5.1 Memory map ................................................................................937

5.18.5.2 Register description .....................................................................937

5.18.6 Register Descriptions (TBD) ..........................................................................938

5.18.6.1 EFUSE_ALL0_INDEX ..................................................................938

5.18.6.2 EFUSE_MODE_CTRL .................................................................939

5.18.6.3 EFUSE_ IP_VER .........................................................................940

5.18.6.4 EFUSE_CFG0 ..............................................................................940

5.18.6.5 EFUSE_NS_EN ...........................................................................941

5.18.6.6 EFUSE_NS_ERR_FLAG .............................................................942

5.18.6.7 EFUSE_FLAG_CLR ....................................................................944

5.18.6.8 EFUSE_NS_MAGIC_NUMBER ...................................................945

5.18.6.9 EFUSE_SEC_EN .........................................................................946

5.18.6.10 EFUSE_SEC_ERR_FLAG ...........................................................947

5.18.6.11 EFUSE_FLAG_CLR ....................................................................948

5.18.6.12 EFUSE_SEC_MAGIC_NUMBER ................................................950

5.18.6.13 EFUSE_FW_CFG ........................................................................950

5.18.6.14 EFUSE_PW_SWT .......................................................................951

5.18.6.15 EFUSE_POR_READ_DATA0 ......................................................952

5.18.6.16 EFUSE_POR_READ_DATA1 ......................................................952

5.18.6.17 EFUSE_POR_READ_DATA2 ......................................................953

5.18.6.18 EFUSE_POR_READ_DATA3 ......................................................953

5.18.6.19 EFUSE_PW_ON_RD_END_FLAG..............................................954

5.18.6.20 EFUSE_NS_S_FLAG ..................................................................954

5.18.6.21 EFUSE_MEM ...............................................................................955

5.18.7 Application Notes ...........................................................................................956

5.18.7.1 Write / Read data .........................................................................956

5.18.7.2 Write .............................................................................................956

5.18.7.3 Read .............................................................................................958

5.18.7.4 Power on read ..............................................................................959

5.18.7.5 Parameterize ................................................................................960

5.18.7.6 Double bit .....................................................................................960

5.18.7.7 BIST .............................................................................................961

5.18.7.8 Lock bits .......................................................................................963

5.18.7.9 Auto Check ...................................................................................966

5.18.7.10 ERROR response ........................................................................966

5.18.8 Implementations .............................................................................................966

UDX710 Device Specification

V1.0 UNISOC Communications, Inc., Confidential and Proprietary 19 of 2899

This document contains information on a product under development.

UNISOC reserves the right to change or discontinue this product without notice.

5.18.9 Future improvements .....................................................................................967

5.19 DVFS .............................................................................................................................967

5.19.1 Overview ........................................................................................................967

5.19.2 Feature ...........................................................................................................967

5.19.3 Parameters .....................................................................................................967

5.19.4 Signals ...........................................................................................................967

5.19.5 Function .........................................................................................................968

5.19.6 Control registers .............................................................................................968

5.19.6.1 Memory map ................................................................................968

5.19.6.2 Register description .....................................................................968

5.19.7 Application notes ............................................................................................968

5.19.8 Implementations .............................................................................................968

5.19.9 Future improvements .....................................................................................968

5.20 I2C .................................................................................................................................968

5.20.1 Overview ........................................................................................................968

5.20.2 Features .........................................................................................................969

5.20.3 Signal Description ..........................................................................................969

5.20.4 Function Description ......................................................................................970

5.20.4.1 System Configuration ...................................................................972

5.20.4.2 Wire Serial Protocol .....................................................................972

5.20.4.3 Arbitration Procedure ...................................................................974

5.20.4.4 Timing Prameters .........................................................................974

5.20.4.5 DMA flow ......................................................................................975

5.20.4.6 Hardware channel mode ..............................................................976

5.20.5 Control Registers ...........................................................................................982

5.20.5.1 Memory map ................................................................................982

5.20.5.2 Register Descriptions ...................................................................985

5.20.5.3 Synchronizer implementation .....................................................1039

5.20.6 Application Notes .........................................................................................1039

5.20.6.1 Skew request check ...................................................................1039

5.20.6.2 Programming Model ...................................................................1040

5.20.6.3 100K mode program examples ..................................................1040

5.20.6.4 400K mode program examples ..................................................1041

5.20.6.5 HS mode program examples .....................................................1041

5.20.6.6 DMA mode program examples ..................................................1041

5.20.6.7 Hardware channel mode program examples .............................1042

5.20.6.8 Hardware channel mode program examples (APB_WR_CMD,

APB_RD_CMD) ...........................................................................................1042

5.20.6.9 Programming Notes ...................................................................1042

5.20.7 Control registers ...........................................................................................1043

5.20.7.1 Memory map ..............................................................................1043

5.20.7.2 Register description ...................................................................1043

5.20.8 Application notes ..........................................................................................1043

5.20.9 Implementations ...........................................................................................1043

5.20.10 Future improvements ...................................................................................1043

5.21 KPD .............................................................................................................................1043

5.21.1 Overview ......................................................................................................1043

5.21.2 Features .......................................................................................................1043

UDX710 Device Specification

V1.0 UNISOC Communications, Inc., Confidential and Proprietary 20 of 2899

This document contains information on a product under development.

UNISOC reserves the right to change or discontinue this product without notice.

5.21.3 Signal Description ........................................................................................1044

5.21.4 Function Description ....................................................................................1045

5.21.5 Control Registers .........................................................................................1048

5.21.5.1 Memory map ..............................................................................1048

5.21.5.2 Register Descriptions .................................................................1049

5.21.6 Application Notes .........................................................................................1063

5.21.7 Control registers ...........................................................................................1064

5.21.7.1 Memory map ..............................................................................1064

5.21.7.2 Register description ...................................................................1064

5.21.8 Application notes ..........................................................................................1064

5.21.9 Implementations ...........................................................................................1064

5.21.10 Future improvements ...................................................................................1064

5.22 AON APB control register ............................................................................................1064

5.22.1 Memory Map ................................................................................................1064

5.22.2 Register Descriptions ...................................................................................1071

5.22.2.1 APB_EB0 ...................................................................................1071

5.22.2.2 APB_EB1 ...................................................................................1074

5.22.2.3 APB_EB2 ...................................................................................1078

5.22.2.4 APB_RTC_EB0 ..........................................................................1081

5.22.2.5 PSCP_AON_EB .........................................................................1082

5.22.2.6 CGM_REG1 ...............................................................................1084

5.22.2.7 CGM_CLK_TOP_REG1 ............................................................1086

5.22.2.8 APCPU_INT_ENABLE_CTRL0 .................................................1088

5.22.2.9 APCPU_INT_ENABLE_CTRL1 .................................................1090

5.22.2.10 APCPU_INT_ENABLE_CTRL2 .................................................1093

5.22.2.11 APCPU_INT_ENABLE_CTRL3 .................................................1096

5.22.2.12 APCPU_INT_ENABLE_CTRL4 .................................................1098

5.22.2.13 APCPU_INT_ENABLE_CTRL5 .................................................1101

5.22.2.14 SP_WAKEUP_MASK_EN0 .......................................................1103

5.22.2.15 SP_WAKEUP_MASK_EN1 .......................................................1107

5.22.2.16 SP_WAKEUP_MASK_EN2 .......................................................1111

5.22.2.17 APB_RST0 .................................................................................1112

5.22.2.18 APB_RST1 .................................................................................1115

5.22.2.19 APB_RST2 .................................................................................1118

5.22.2.20 APB_RST3 .................................................................................1121

5.22.2.21 CM4_SYS_SOFT_RST .............................................................1122

5.22.2.22 PSCP_SOFT_RST ....................................................................1123

5.22.2.23 NRCP_SOFT_RST ....................................................................1125

5.22.2.24 V3PS_SOFT_RST .....................................................................1126

5.22.2.25 V3PHY_SOFT_RST ..................................................................1127

5.22.2.26 WDG_RST_FLAG ......................................................................1127

5.22.2.27 APCPU_SOFT_RST ..................................................................1129

5.22.2.28 BOOT_MODE ............................................................................1129

5.22.2.29 CP_ARM_JTAG_CTRL .............................................................1130

5.22.2.30 RC100M_CFG ...........................................................................1131

5.22.2.31 CCIR_RCVR_CFG.....................................................................1132

5.22.2.32 PLL_BG_CFG ............................................................................1134

5.22.2.33 MBIST_EFUSE_CTRL ...............................................................1135

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