Technical Specification
1
© 25/50 Gigabit Ethernet Consortium Members 2014 - 2019. Distribution limited under Consortium rules.
Table of Contents
1 Overview ................................................................................................................................. 1
2 Standards Reference ............................................................................................................... 1
3 Low Latency Forward Error Correction (LL-FEC) ..................................................................... 2
3.1 LL-FEC Details ................................................................................................................... 3
3.1.1 Generator Polynomial ............................................................................................... 3
3.1.2 Message Polynomial ................................................................................................. 3
3.1.3 Parity Polynomial ...................................................................................................... 3
3.1.4 FEC Input Symbols ..................................................................................................... 3
3.2 10-bit Pad Symbol ............................................................................................................ 3
3.3 Symbol Distribution .......................................................................................................... 3
3.4 Alignment Marker Insertion Period ................................................................................. 7
3.5 Autonegotiation ............................................................................................................... 7
3.5.1 Consortium Next Page Format.................................................................................. 7
3.5.2 Autonegotiation Resolution ...................................................................................... 8
3.6 Annex A [Informative]: Error Correcting Performance of RS(272) .................................. 8
3.6.1 Performance of LL-FEC with 50, 100GE PHYs ........................................................... 9
3.6.2 Performance of LL-FEC with 200GE PHYs ............................................................... 10
3.7 Annex B [Informative]: Example RS(272) Codewords .................................................... 11
List of Figures
Figure 1 - 50GE Transmit Bit Ordering ............................................................................................ 4
Figure 2 - 100GE Transmit Bit Ordering .......................................................................................... 5
Figure 3 - 200GE Transmit Bit Ordering .......................................................................................... 6
Figure 4 - Unformatted OUI Next Page, Showing Additional Fields for LL-FEC .............................. 7
Figure 5 - RS(544) Single Part Link Performance (50, 100GE) ........................................................ 9
Figure 6 - RS(272) Single Part Link Performance (50, 100GE) ........................................................ 9
Figure 7 - RS(544) Single Part Link Performance (200GE) ............................................................ 10
Figure 8 - RS(272) Single Part Link Performance (50, 100GE) ...................................................... 11
1 Overview
This specification provides functional details for instantiation of forward error correction based
on a shortened Reed Solomon code, RS(272).
2 Standards Reference
References are made throughout this document to IEEE 802.3-2015 Ethernet Access Method
and Physical Layer [base standards]. It should be noted that at the time of publication of this