2020亚洲固态电路会议特辑：集成电路设计进展

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"JSSC_202110 - IEEE Journal of Solid-State Circuits 的 2021年10月刊，专注于固态电路的晶体管级集成电路设计" 在这一期的《IEEE固态电路期刊》(JSSC)中，特别关注了2020年亚洲固态电路会议(A-SSCC)的相关内容。这个专业期刊发表的文章涵盖了固态电路领域的广泛主题，特别是关于集成电路的晶体管级设计。编辑部新增了P.K.Hanumolu作为副编辑，增强了期刊的专业阵容。本期的客座编辑R.C.-H.Chang、W.-Z.Chen和J.Deguchi介绍了2020年亚洲固态电路会议的特辑，该会议是固态电路技术的重要交流平台，展示了亚洲在该领域的最新研究成果和技术趋势。在特辑论文中，有几篇引人注目的文章： 1. M.Kim和S.H.Cho的论文提出了一种利用镜像极点进行频率补偿的单BJT带隙基准源，这可能代表着新型低功耗、高性能基准源设计的进步。 2. J.S.Y.Tan等人介绍了一种完全能源自给的温度到时间转换器，它由摩擦电能收集器供电，用于生物医学应用。这种创新设计可以实现自给自足的能源管理和精确的温度监测。 3. J.Zhao等人的工作展示了一款仅310纳安静态电流、3-fs频率上限的全集成无电容时域LDO（低压差稳压器），具有事件驱动的充电泵和前馈瞬态增强功能，提升了电源管理的效率和响应速度。 4. H.-C.Cheng等人设计了一种可重构的电容式功率转换器，通过电容再分配技术，适用于室内光能供电的无电池物联网设备，解决了无电池系统能量采集和转换的挑战。 5. ACT2–2MASH ADC（模数转换器）由Y.Gao等人提出，其基于多速率LMS（最小均方误差）的背景校准方法，实现了高精度和灵活性的信号转换，对于现代通信系统和数据采集系统具有重要意义。这些论文代表了固态电路设计的前沿技术，涵盖了能源管理、基准源、低功耗稳压器、无线传感器网络的能源采集以及高精度ADC等多个方面，对研究者和工程师了解和推动集成电路设计的发展提供了宝贵的参考。

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3078 IEEE JOURNAL OF SOLID-STAT E CIRCUITS, VOL. 56, NO. 10, OCTOBER 2021

an mm-wave front-end to cover this frequency band with suf-

ﬁcient output power, excellent linearity, low-noise ﬁgure (NF),

compact size, robust package, and EVM requirement for the

IEEE 802.11aj requirement.

IEEE 802.11aj is devised for high data rate wireless personal

area network (WPAN) [24] and also for the portable device.

The system requires high linearity for the transmitter and low

NF for the receiver. For the system, it also requires low power

consumption, compact size, and wideband [11], [16], [25],

[26]. The direct-conversion topology has the advantage of the

system’s simplicity, compact size, and low-power consump-

tion. However, direct-conversion topology also suffers from

the local oscillator (LO) leakage and im age frequ e ncy signal.

Therefore, to achieve a direct-conversion system at 45 GHz

with 64 QAM, it is quite crucial to introduce LO leakage

suppression and image frequency signal suppression units.

In this work, we present a world-ﬁrst IEEE 802.11aj

mm-wave I/Q transceiver front-end system targeted at support-

ing 64 QAM with Yagi-Uda antenna, operating from 42.3 to

48.4 GHz, in a 120-nm SiGe:C BiCMOS process. The pro-

posed system is comprised of a transmitter, a receiver, and two

onboard substrate integrated waveguide (SIW)-fed Yagi-Uda

antennas. The Yagi-Uda antennas are integrated with the trans-

mitter and receiver chips using broadband wire-bond intercon-

nections, which results in a low-cost solution. At mm-wave

frequency, the common-mode (CM) issue in a differential

system could degr ade the system linearity, system gain, and

introduce instability. In this work, the CM effect caused by

transformer-based balun is analyzed. Based on the analysis,

a fast impedance equalization with a passive component com-

pensation method is proposed to cope with this issue in a

short cycle, which effectively improves the linearity of the

transmitter. Also, a T -type second-order harmonic termination

method is applied at the output of the power ampliﬁer (PA) to

further improve the linearity of the transmitter. Furthermore,

a self-mixing method is adopted to the power detector (PD)

of the tran smitter output to have closer monitoring on the

down-converted LO leakage term and image signal, which

is used for LO leakage and image signal calibration. With

all the proposed methods, the transmitter achieves an OP

1dB

of 14.6–16.4 dBm and a conversion gain (CG) of 24 dB

at the IEEE 802.11aj frequency band. The receiver achieves

3.8–4.1-dB NF and −18.7- to −22-dBm input 1-dB compres-

sion point, while the CG is 43.8 dB. In the wireless data

transmission test, the system delivers a measured transmitter-

to-receiver EVM with 64 QAM better than −28.5 dB at a

1-m distance over the IEEE 802.11aj frequency band. The

power consumption is 438 and 186 mW in the transmitter and

receiver modes, respectively.

This chipset is ﬁrst reported in [27], and this article

presents a detailed design methodology. This article is orga-

nized as follows. Section II introduces the IEEE 802.11aj

direct-conversion transceiver architecture. Section III presents

the model to analyze the CM effect in transformer-based

balun and the proposed method. Section IV d escribes the

transceiver circuit design methodology, and the package design

methodology is provided in Section V. Section VI reports

the measurement results for the entire transceiver system.

Section VII draws conclusions.

TABLE I

ASIC LINK BUDGET PARAMETERS FOR SHORT-RANGE COMMUNI CATION

Fig. 1. Block diagram of the 45-GHz direct-conversion (a) transmitter and

(b) receiv er.

II. 45-GHz TRANSCEIVER SYSTEM ARCHITECTURE

Table I shows a short-range communication link budget

example of the 45-GHz transceiver. According to the IEEE

802.11aj standard [23], the receiver sensitivity of a typical

45-GHz receiver is −53 dBm for SC 64-QAM signals (modu-

lation and coding scheme index 7), and the minimum required

EVM is −26 dB at the receiver side. For a typical 45-GHz

transceiver shown in Table I, the received signal strength at

a 1-m distance is calculated to b e −47.5 dBm, which is

about a 5.5-dB margin from the receivers’ sensitivity. Besides,

the communication distance could be extended by using a high

gain antenna or multiantenna array conﬁguration.

Fig. 1 shows the simpliﬁed block d iagram of this IEEE

802.11aj 45-GHz transceiver. A direct conversion architec-

ture is employed for both the transmitter and the receiver

for wide-bandwidth requirements [28] and low-power con-

sumption for the next step on phased array integration. The

transmitter, the receive r, and the antenna are implemented with

the system-on-board solution to improve transceiver isolation

and avoid signal coupling from the antenna switching unit.

The mixer-ﬁrst topology is adopted for the transmitter to

obtain wideband gain characteristics with low-power con-

sumption [16]. The printed onboard Yagi-Uda antenna is

proposed to achieve a compact size. At the transmitter output,

the self-mixing m ethod is app lied to have a better LO leakage

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ZHOU et al.: −28.5-dB EVM 64-QAM 45-GHz TRANSCEIVER FOR IEEE 802.11aj 3079

Fig. 2. Compact model of a 1:1 transformer with ﬂoating outputs.

monitoring from the down-converted LO leakage term and

image signal suppression from the down-converted image

signal term.

The transmitter consists of an 8-bit phase shifter (PS) for

input I/Q signal phase mismatch calibration, an up-conversion

mixer with a 6-bit dc-offset tuning unit for the LO leakage cali-

bration, a variable gain ampliﬁer (VGA) with 6-bit g ain control

for the amplitude mismatch calibration of I/Q signal, a self-

mixing method-based PD for LO leakage and image frequency

detection, and a high linearity PA to amplify the modulated

signal. The receiver comprises a single-ended low-noise ampli-

ﬁer (LNA), a PS, a VGA, a current-mode down-conversion

mixer with an intermediate frequency (IF) buffe r to d eliver the

IF output signal, and an LO driver ampliﬁer. In this transceiver

design, the differential architectu re is applied to all th e blocks

besides LNA, VGA, and LO driver ampliﬁer to ensure stability

and even-order distortion suppression in a direct conversion

system.

III. A

NALY S I S OF CM SIGNAL IN

TRANSFORMER-BASED BALUN

Transformers have been used on-chip for their capabil-

ity of achieving impedance transfer, conversion from the

single-ended signal to differential signals, and dc isolation

in one device [29]. By connecting one terminal at the sec-

ondary side to the ground, it becomes a transformer-based

balun that can convert the single-ended signal to differential

signals [30]. However, due to the introduction of ground, some

unwanted CM voltage o ccurs at the differential ports of the

transformer-based balun. Because of this effect, the diff eren-

tial pair that d rives the transformer-based balun experiences

different voltage magnitudes relative to the ground for both

differential outputs. When such a transformer-based balun is

applied to the output of a differential structure PA, it will

deteriorate the output 1-dB compression point as one-half of

the differential ports do not have their full voltage-swing at

this 1-dB compression point.

Fig. 2 shows an ideal model of a 1:1 transformer with

ﬂoating output, where the primary side is driven by two

differential current sources, and all the relevant parasitics are

included [30]. The interwinding capacitance c

is in cluded

in the model to analyze the behav ior for the CM effect at

the input. When the output ports are ﬂoating, the circuit is

completely symmetrical, and the input port impedances Z

and Z

are equal to each other. Therefore, the voltages v

Fig. 3. Mixed-mode port of a compact 1:1 transformer.

and v

and currents i

and i

only exist in the differential

mode (DM), and no CM voltage is present at the input. Then,

we explain this phenomenon by dividing the voltages and

currents into DM and CM components. It is necessary to

understand the CM voltages that occur at the differential ports

of the transformer-based balun. According to Fig. 2, the DM

)andCM(v

) voltages and the DM (i

)andCM(i

)

currents can be calculated. The currents i

and i

present a

similar principle, and this results in a zero value v

and i

This is only suitable for ideal symmetrical networks. When the

structure is asymmetric, such a method is no longer available.

Therefore, a more detailed analysis is now presented with

the mixed-mode parameters [31]. The mixed-mode ports

are derived from Fig. 2, and the equivalent mixed-mode

model is illustrated in Fig. 3. Mixed-mo de port 1 consists

of single-ended ports 1 and 2, and mixed-mode port 2 is

composed of single-ended ports 3 and 4. The mixed-mode

ports have the beneﬁt that the signals at the two ports are

decomposed into a DM part and a CM part, which provides

more insight into the symmetry problem [32]. In general, each

port supports the propagation of both DM and CM signals.

Then, the response of the differential circuit to a stimulus can

be expressed with a standard Z -matrix Z

(4 × 4), and this

matrix relates the DM/CM currents to the DM/CM voltages.

Thus, we can get the expression of the mixed-mode Z-matrix

as follows:

⎡

⎢

⎣

⎤

⎥

⎦



][Z

]

][Z

]



⎡

⎢

⎣

⎤

⎥

⎦

. (1)

From (1), the CM voltage (v

) at mixed-mode port 1 can

be found as follows:

= Z

cd11

+ Z

cd12

+ Z

cc11

+ Z

cc12

. (2)

Because ports 3 and 4 in Fig. 2 are ﬂoating outputs, which

is equ ivalent to i

= i

= 0, according to Fig. 2, we can get

that i

= i

= 0, and then, the expression of v

can be

deduced as

= Z

cd11

+ Z

cc11

. (3)

The current i

can be expressed in terms of voltage v

follows:

= i

+ i

−(v

+ v

)

−2v

. (4)

Through combining (3) and (4), the expression of v

can be

written as

cd11

+ 2Z

cc11

. (5)

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3080 IEEE JOURNAL OF SOLID-STAT E CIRCUITS, VOL. 56, NO. 10, OCTOBER 2021

Fig. 4. (a) Cross-sectional view of the metal layer and (b) 3-D view

of the transformer-based single-turn vertical coupling 1:1 balun with the

compensated MIM capacitor.

It can be concluded from (5) that, to set the undesired CM

voltage at zero, Z

cd11

must equals zero. As can be seen

from (1), Z

cd11

represents the transimpedance conversion from

the DM current at mixed-mode port 1 to the CM voltage at

the same port, that is

cd11

− Z

+ Z

− Z

. (6)

Because a transformer is a passive network, that is, Z

= Z

the requirement for zero CM voltage at the input equals

= Z

. (7)

When the circuit is symmetric, this condition is satisﬁed,

as shown in Fig. 2. Thus, this analysis shows that there is

no CM voltage at the input, which is the same as expected.

By performing such analysis, we have a deeper understanding

of the conditions required for no CM voltage at the input.

However, when one of the ﬂoating ports is shorted to

ground for forming a transformer-based balun, the condition

in (7) is no longer met due to the asymmetry. To satisfy

this requirement and reduce the impact of CM voltage on the

differential circuit, an extra component needs to be added to

compensate for the difference between input impedances and

fulﬁll the requirement of (7) again.

In an asymmetric transformed-based balun or the Marchand

balun, the CM effect arises due to the introduced unbalanced

ground port, and this effect can introduce the DM-to-CM

issue [29], [33], [34]. In the previous analysis, a mathematic

requirement is derived, and an extra component could balance

the equation and fulﬁll (7) again. In our design, we ﬁrst

keep the real part the same and add a passive component to

change the image part. Based on this principle, a compensated

capacitor is applied, as shown in Fig. 4.

Fig. 5 shows the equivalent circuit model of the transformer

with the compensated capacitor. We use DM and CM analysis

methods to analyze the transformer-based balun [34]. Through

the analysis of the CM model, the mechanism by which

the compensation capacitor adjusts the CM voltage can be

obtained. In turn, the optimal compensation capacitor value

can be obtained to minimize the effect of the CM voltage on

the transformer-based balun.

Fig. 6(b) presents the equivalent half circuit model of the

transformer-based balun in the CM mode. As derived from

Fig. 6(b), we can get the Z matrix of the equivalent two-port

CM circuit n etwork (see Appendix A). Therefore, S

of the

Fig. 5. Equivalent circuit model of the transformer-based balun with the

compensated MIM capacitor.

Fig. 6. Equivalent half circuit model of the transformer-based balun in

(a) DM model and (b) CM model.

two-port network can be derived [35], the expression of which

is as follows:

√

· R

+ Z

)(Z

+ Z

) − Z

. (8)

In order to suppress the CM signal to the balanced differen-

tial output ports, the CM signal should not transfer from port 1

) to port 2 (P

, P

), as illustrated in Fig. 6(b). Thus, it can

be concluded from (12) that, for a given transformer-based

balun, there is an optimal C

comp

value (when th e condition

= 0 is satisﬁed), which can minimize the CM signal effect

at the balanced differential output ports. Also, the expression

of C

comp

can be deduced as (9).

Fig. 4(b) shows a transformer-based balun, and the trans-

former is composed of the top-two m etal layers AM and LY

to enhance the coupling and reduce the ohmic loss. Port 4

) is connected with the ground to form a single input.

A compensated capacitor (C

comp

) is inserted at the center

of the b alanced differential ports (P

, P

). An estimated

initial capacitance value of 1.5 p F at 45 GHz is adopted

in our design according to (9). The exact value (1.6 pF at

45 GHz) of the compensation capacitor is determined based

on the post-layout simulation, and the deviation from the initial

value obtained from (9) is acceptable. The differential output

impedance of the transformer-based balun with and without

the compensated capacitor is illustrated in Fig. 7. It can

be deduced that, with the introduction of the compensated

capacitors for fast impedance equalization, the requirements

in (7) are fulﬁlled. Fig. 8(a) and ( b) shows the simulated

differential output voltages of the transformer-based b alun

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ZHOU et al.: −28.5-dB EVM 64-QAM 45-GHz TRANSCEIVER FOR IEEE 802.11aj 3081

Fig. 7. Differential output impedance of the transformer-based balun

(a) without and (b) with the compensated capacitor.

with swept input power at 45 GHz. By comparison, it can be

found that, after using this capacitor for compensation, the CM

signal problem at the balun differential output ports has been

greatly dealt with. Besides, Fig. 8(c) depicts the simulated

phase and amplitude imbalance at the differential ports of the

transformer-based single-turn vertical coupling 1:1 balun with

the metal width of 12 μm, as shown in Fig. 4(b). It is noted

that the balun suffers from an obvious balance problem in both

the amplitude and phase before capacitance compensation.

By introducing the compensation capacitor, the amplitude and

phase imbalance will be dramatically improved.

IV. C

IRCUIT DESIGN METHODOLOGY

In this section, we will present the circuit design method-

ology of the 45-GHz transceiver system, including the con-

sideration of each block, and then present the simulated and

measured results of key building blocks.

A. PA

In the 802.11aj frequency band, the PA needs to operate

at 6-dB back-off region to ensure efﬁciency and meet the

linearity requirement of −26-dB EVM. Thus, the PA requires

not only high saturated output power and high power-added

efﬁciency (PAE) but also high linear ity. Based on those

considerations, this PA is biased in class-AB mode to get

linearity close to the saturation region as the previous design

for 3G and 4G wireless communication systems. However,

as the conduction angle of output current decreases (compared

with class-A mode), the second-harmonic current component

of the PA increases, which will greatly deteriorate the linearity

of the PA.

As shown in Fig. 9, this PA is a two-stage differential

cascode ampliﬁer biased at the deep class-AB mode with the

current density of 1.2 mA/μm. Due to this deep class-AB

mode, the second-order harmonic at the PA output inﬂuences

the output performance, especially on the output 1-dB com-

pression point. As the PA is a differential topology, each

of the even harmonic components can be eliminated by the

Fig. 8. Output voltage of the differential ports (P

, P

) with swept

input power at 45 GHz (a) before and (b) after capacitance compensation.

capacitance compensation.

natural RF virtual ground, but this does not apply to odd

harmonic components. In our design, a T -network formed

by a transmission line-based inductor L

(L = 110 μm;

W = 4 μm) and two MIM capacitors (C

) is adopted at

the output of the PA to achieve a low impedance path

for forming a second-order harmonic short [36]. With this

method, the output power of the fundamental frequency is

not affected since the transmission line is virtually grounded

comp

≈

−4w

(2r

+ 2L

+ L

) + j (M + 2C

) + 4wC



(2r

+ 2L

+ L

− 4M)

− (M + C

)

[jC

+ L

)(r

+ L

) − 2( j wC

+ M) + 4(r

+ L

)]

(9)

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3082 IEEE JOURNAL OF SOLID-STAT E CIRCUITS, VOL. 56, NO. 10, OCTOBER 2021

Fig. 9. Schematic of the PA with second-order harmonic termination method.

Fig. 10. Fundamental and second-order harmonic current of the PA before

and after LI.

at odd-order harmonics. As shown in Fig. 10, the second-

order harmonic current is well improved after adopting this

linearity improvement (LI) method. The interstage matching

of the PA is realized by a 1:1 turn ratio transformer together

with a short transmission line connected in series between

the output of the ﬁrst stage and the transformer. The input

and output impedance matching networks are achieved by the

transformer-based balun mentioned in Section III. It is worth

mentioning that, different from the input balun (Balun I), due

to the introduction of the dc feeder Z

feed

, when designing the

output balun (Balun II), the length of the dc feeder needs to

be long to avoid parallel r esonance between the dc feeder and

the compensation capacitor C

comp

. As the balun adopts the

proposed CM signal suppression technology, the linearity of

the PA has been further improved.

The measured peak gain of the PA is 24.5 dB at 46 GHz.

Also, it has over 23.5 dB from 42 to 49 GHz, as illustrated

in Fig. 11(a). Compared with the simulation results (the dashed

line represents the simulation results, and the solid line stands

for the measured results), the diff erence between simulation

and measurement can be contribu ted by inaccurate modeling

of the transistor substrate network at this frequency. Fig. 11

also shows that the measured peak output 1-dB compression

point (OP

1dB

) of the PA is 16.8 dBm at 44 GHz, and OP

1dB

is higher than 15.7 dBm between 42 and 49 GHz. The dc

power consumption of the PA is 230 mW under 3.3-V bias.

Besides, the simulated OIP3 of the PA is around 26 dB over the

IEEE 802.11aj frequency band. The test results show that the

Fig. 11. (a) Simulated and measured S-parameters and output 1-dB

compression point. (b) Measured output power and gain with input power

at 45 GHz of the PA.

Fig. 12. Schematic of (a) GCU and (b) PS.

difference between the fundamental signal of the transmitter

and the third-order intermodulation component is 34.16 dB.

B. PS

The image frequency generated by the I/Q signal mismatch

will seriously deteriorate the EVM o f the direct conversion

system, which will affect the modulation order of the system.

In our design, a self-mixing method is applied to the PD.

By applying the self-mixing method, the output of the PD

contains a spectrum ( f

- f

) that can be used to detect

the information of the image frequency. With this frequency

information, the PS is adopted to calibrate the phase mismatch

of I /Q signals that result in the generation of image frequency

signal.

The topology of the PS is based on our previous design [37],

and the block diagram of the PS is depicted in Fig. 12.

Since the PS in the transmitter is used to compensate for

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