6.6 I
2
C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see 图 7-1)
STANDARD-MODE
I
2
C BUS
FAST-MODE
I
2
C BUS
UNIT
MIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHz
t
sch
I
2
C clock high time 4 0.6
μs
t
scl
I
2
C clock low time 4.7 1.3
μs
t
sp
I
2
C spike time 50 50 ns
t
sds
I
2
C serial-data setup time 250 100 ns
t
sdh
I
2
C serial-data hold time 0
(1)
0
(1)
μs
t
icr
I
2
C input rise time 1000 20 + 0.1C
b
(2)
300 ns
t
icf
I
2
C input fall time 300 20 + 0.1C
b
(2)
300 ns
t
ocf
I
2
C output fall time (10-pF to 400-pF bus) 300 20 + 0.1C
b
(2)
300 ns
t
buf
I
2
C bus free time between stop and start 4.7 1.3
μs
t
sts
I
2
C start or repeated start condition setup 4.7 0.6
μs
t
sth
I
2
C start or repeated start condition hold 4 0.6
μs
t
sps
I
2
C stop condition setup 4 0.6
μs
t
vdL(Data)
Valid-data time (high to low)
(3)
SCL low to SDA output low valid 1 1
μs
t
vdH(Data)
Valid-data time (low to high)
(3)
SCL low to SDA output high valid 0.6 0.6
μs
t
vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
1 1
μs
C
b
I
2
C bus capacitive load 400 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V
IH
min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) C
b
= total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see 图 7-1).
6.7 Switching Characteristics
over recommended operating free-air temperature range, C
L
≤ 100 pF (unless otherwise noted) (see 图 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
t
pd
(1)
Propagation delay time
R
ON
= 20 Ω, C
L
= 15 pF
SDA or SCL SDn or SCn
0.3
ns
R
ON
= 20 Ω, C
L
= 50 pF
1
t
iv
Interrupt valid time
(2)
INTn INT 4
μs
t
ir
Interrupt reset delay time
(2)
INTn INT 2
μs
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) Data taken using a 4.7-kΩ pull-up resistor and 100-pF load (see 图 7-2).
6.8 Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
PWRL
Low-level pulse duration rejection of INTn inputs
(1)
1
μs
t
PWRH
High-level pulse duration rejection of INTn inputs
(1)
0.5
μs
(1) Data taken using a 4.7-kΩ pull-up resistor and 100-pF load (see 图 7-2).
PCA9544A
ZHCSK60G – OCTOBER 2005 – REVISED MARCH 2021
www.ti.com.cn
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