IDT高速TeraSync FIFO存储器规格详细解析

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"C1547672_FIFO存储器规格书(瑞萨)_IDTFIFO存储器规格书.PDF" 本文档详细介绍了IDT公司的一系列高速TeraSync FIFO存储器，包括不同配置下的18位和9位内存组织结构。这些器件主要用于高速数据同步和缓冲，适用于各种工业和商业应用。文档中列出的具体型号有IDT72T1845、IDT72T1855、IDT72T1865、IDT72T1875、IDT72T1885、IDT72T1895、IDT72T18105、IDT72T18115以及IDT72T18125。这些FIFO存储器提供了多种容量选择，从2,048x18到524,288x18位，以及对应的9位配置。这些容量选项允许设计者根据系统需求灵活选择合适的存储容量。例如，IDT72T1845提供2,048x18位的配置，而IDT72T18125则支持高达524,288x18位的存储。这些FIFO的主要特点包括： 1. 高速操作：这些器件设计用于处理高速数据流，确保数据在不同速度的系统组件之间顺畅传输。 2. TeraSync技术：TeraSync是IDT的专利技术，它提供精确的时钟同步，确保数据在多个设备间准确无误地传递。 3. 多种配置：用户可以根据需要选择18位或9位宽的数据总线，以及不同的存储深度，满足不同系统的接口需求。 4. 宽工作温度范围：这些FIFO适用于商业和工业环境，具有可靠的温度性能范围，保证了在各种条件下稳定运行。 5. EOL（End-of-Life）通知：部分型号如标注星号(*)的产品已进入生命周期末期，最后购买期限为2018年5月26日，提醒用户及时进行库存管理和替换方案规划。这些FIFO存储器在设计时考虑了灵活性、性能和可靠性，是高速数据处理系统中的关键组件，例如在通信设备、数据采集系统、图像处理和嵌入式系统等应用中都能发挥重要作用。设计人员应根据具体的应用需求和系统规格，选择合适的IDT72T系列FIFO产品，以实现最佳的系统性能和稳定性。

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

Symbol Rating Commercial Unit

TERM Terminal Voltage –0.5 to +3.6

(2)

with respect to GND

TSTG Storage Temperature –55 to +125 °C

IOUT DC Output Current –50 to +50 mA

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 2.375 2.5 2.625 V

GND Supply Voltage 0 0 0 V

IH Input High Voltage ⎯ LVTTL 1.7 — 3.45 V

⎯ eHSTL V

REF+0.2 — VDDQ+0.3 V

⎯ HSTL VREF+0.2 — VDDQ+0.3 V

IL Input Low Voltage ⎯ LVTTL -0.3 — 0.7 V

⎯ eHSTL -0.3 — VREF-0.2 V

⎯ HSTL -0.3 — VREF-0.2 V

REF

(1)

Voltage Reference Input ⎯ eHSTL 0.8 0.9 1.0 V

⎯ HSTL 0.68 0.75 0.9 V

TA Operating Temperature Commercial 0 — 70 °C

TA Operating Temperature Industrial -40 — 85 °C

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. VCC terminal only.

NOTE:

1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. Outputs are not 3.3V tolerant.

Symbol Parameter

(1)

Conditions Max. Unit

(2,3)

Input VIN = 0V 10

(3)

Capacitance

OUT

(1,2)

Output VOUT = 0V 10 pF

Capacitance

CAPACITANCE (TA = +25°C, f = 1.0MHz)

NOTES:

1. With output deselected, (OE ≥ V

IH).

2. Characterized values, not currently tested.

3. C

IN for Vref is 20pF.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol Parameter Min. Max. Unit

LI Input Leakage Current –10 10 μA

ILO Output Leakage Current –10 10 μA

(5)

Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V

IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V

IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V

OL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V

IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V

IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V

IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895

ICC1

(1,2)

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 40 mA

I/O = HSTL — 60 mA

I/O = eHSTL — 60 mA

CC2

(1)

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 10 mA

I/O = HSTL — 50 mA

I/O = eHSTL — 50 mA

IDT72T18105/72T18115/72T18125

ICC1

(1,2)

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 50 mA

I/O = HSTL — 70 mA

I/O = eHSTL — 70 mA

ICC2

(1)

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA

I/O = HSTL — 60 mA

I/O = eHSTL — 60 mA

NOTES:

1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.

2. For the IDT72T18105/72T18115/72T18125, typical ICC1 calculation (with data outputs in Low-Impedance):

for LVTTL I/O ICC1 (mA) = 1.0 x fs, fs = WCLK = RCLK frequency (in MHz)

for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.0 x fs), fs = WCLK = RCLK frequency (in MHz)

For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, typical ICC1 calculation (with data outputs in Low-Impedance):

for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)

for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).

3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)

with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000

fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,

N= Number of outputs switching.

4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).

5. Outputs are not 3.3V tolerant.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

AC ELECTRICAL CHARACTERISTICS

(1)

⎯ SYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

Commercial Com’l & Ind’l

(2)

Commercial Commercial

IDT72T1845L4-4 IDT72T1845L5 IDT72T1845L6-7

IDT72T1855L4-4 IDT72T1855L5 IDT72T1855L6-7

IDT72T1865L4-4 IDT72T1865L5 IDT72T1865L6-7

IDT72T1875L4-4 IDT72T1875L5 IDT72T1875L6-7

IDT72T1885L4-4 IDT72T1885L5 IDT72T1885L6-7

IDT72T1895L4-4 IDT72T1895L5 IDT72T1895L6-7

IDT72T18105L4-4 IDT72T18105L5 IDT72T18105L6-7 IDT72T18105L10

IDT72T18115L4-4 IDT72T18115L5 IDT72T18115L6-7 IDT72T18115L10

IDT72T18125L4-4 IDT72T18125L5 IDT72T18125L6-7 IDT72T18125L10

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fC Clock Cycle Frequency (Synchronous) — 225 — 200 — 150 — 100 MHz

tA Data Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns

tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns

tCLKH Clock High Time 2.0 — 2.3 — 2.8 — 4.5 — ns

tCLKL Clock Low Time 2.0 — 2.3 — 2.8 — 4.5 — ns

tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns

tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns

tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns

tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns

tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns

tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns

tWCSS WCS setup time 1.2 — 1.5 — 2.0 — 3.0 — ns

tWCSH WCS hold time 0.5 — 0.5 — 0.5 — 0.5 — ns

fS Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 MHz

tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns

tSCKH Serial Clock High 45 — 45 — 45 — 45 — ns

tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns

tSDS Serial Data In Setup 15 — 15 — 15 — 15 — ns

tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns

tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns

tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns

tRS Reset Pulse Width

(3)

30 — 30 — 30 — 30 — ns

tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns

tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — μs

tRSR Reset Recovery Time 10 — 10 — 10 — 10 — ns

tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns

tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns

tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns

tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns

tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3.6 — 3.8 — 4.5 ns

tERCLK RCLK to Echo RCLK output — 3.8 — 4 — 4.3 — 5 ns

tCLKEN RCLK to Echo REN output — 3.4 — 3.6 — 3.8 — 4.5 ns

tRCSLZ RCLK to Active from High-Z

(4)

— 3.4 — 3.6 — 3.8 — 4.5 ns

tRCSHZ RCLK to High-Z

(4)

— 3.4 — 3.6 — 3.8 — 4.5 ns

tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5—4—5—7—ns

SKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6—8—ns

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