7
TCA9548A
www.ti.com.cn
ZHCSA11G –MAY 2012–REVISED NOVEMBER 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Electrical Characteristics
(1)
(continued)
V
CC
= 1.65 V to 5.5 V, over recommended operating free-air temperature ranges supported by Recommended Operating
Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(2)
MAX UNIT
(5) C
io(ON)
depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
C
io(off)
(5)
SDA
V
I
= V
CC
or GND
(3)
, Switch OFF 1.65 V to 5.5 V
20 28
pF
SC7–SC0, SD7–SD0 5.5 7.5
R
ON
Switch-on resistance
V
O
= 0.4 V, I
O
= 15 mA
4.5 V to 5.5 V 4 10 20
Ω
3 V to 3.6 V 5 12 30
V
O
= 0.4 V, I
O
= 10 mA
2.3 V to 2.7 V 7 15 45
1.65 V to 1.95 V 10 25 70
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see 图 6)
(3) C
b
= total bus capacitance of one bus line in pF
6.6 I
2
C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see 图 5)
MIN MAX UNIT
STANDARD MODE
f
scl
I
2
C clock frequency 0 100 kHz
t
sch
I
2
C clock high time 4 μs
t
scl
I
2
C clock low time 4.7 μs
t
sp
I
2
C spike time 50 ns
t
sds
I
2
C serial-data setup time 250 ns
t
sdh
I
2
C serial-data hold time 0
(1)
μs
t
icr
I
2
C input rise time 1000 ns
t
icf
I
2
C input fall time 300 ns
t
ocf
I
2
C output (SDn) fall time (10-pF to 400-pF bus) 300 ns
t
buf
I
2
C bus free time between stop and start 4.7 μs
t
sts
I
2
C start or repeated start condition setup 4.7 μs
t
sth
I
2
C start or repeated start condition hold 4 μs
t
sps
I
2
C stop condition setup 4 μs
t
vdL(Data)
Valid-data time (high to low)
(2)
SCL low to SDA output low valid 1 μs
t
vdH(Data)
Valid-data time (low to high)
(2)
SCL low to SDA output high valid 0.6 μs
t
vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
1 μs
C
b
I
2
C bus capacitive load 400 pF
FAST MODE
f
scl
I
2
C clock frequency 0 400 kHz
t
sch
I
2
C clock high time 0.6 μs
t
scl
I
2
C clock low time 1.3 μs
t
sp
I
2
C spike time 50 ns
t
sds
I
2
C serial-data setup time 100 ns
t
sdh
I
2
C serial-data hold time 0
(1)
μs
t
icr
I
2
C input rise time
20 + 0.1C
b
(3)
300 ns
t
icf
I
2
C input fall time
20 + 0.1C
b
(3)
300 ns
t
ocf
I
2
C output (SDn) fall time (10-pF to 400-pF bus)
20 + 0.1C
b
(3)
300 ns
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