PowerPC Linux编程指南：EIS支持的e500/e200处理器详解

powerpc

linux

需积分: 10 130 浏览量更新于2024-07-18 收藏 6.13MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

《PowerPC Linux编程手册》是一本专门为Freescale Power Architecture处理器（包括e500系列如e500v1、e500v2、e500mc、e5500和e6500，以及e200系列）的编程者编写的参考指南，适用于Rev.1版本的EIS2.1。本书旨在提供深入理解和实用指导，帮助开发者在PowerPC架构上进行Linux开发。该手册分为多个章节，首先介绍了Power Architecture技术及其Freescale Embedded Implementation Standards (EIS)的概述。EIS是Freescale对Power Architecture体系结构的定制实现，它定义了硬件和软件接口的一致性，确保了不同产品之间的兼容性。 1.1节着重讲解了EIS的不同版本，以及读者如何区分书中的内容与EIS或EREF规范结构。EIS v1是一个基础，而后续版本可能包含了更多特性与改进。作者鼓励读者理解这些版本的区别，以便更好地利用手册提供的信息。章节1.1.3深入探讨了Power ISA类别，这是Power Architecture的核心概念，分为三个主要部分：基础类别、嵌入式类别和服务器类别。基础类别提供了通用的指令集和架构支持，而嵌入式和服务器类别则针对特定应用环境进行了优化，比如嵌入式系统和高性能服务器。 1.1.4部分讲述了Power Architecture技术的发展历程，包括技术演进的关键点和Freescale在这个过程中的角色。这有助于读者了解PowerPC在Linux开发中的历史背景和当前地位。此外，手册还提供了一些指南，如如何使用本书、目标读者群体、组织结构以及推荐的相关阅读材料，确保读者能有效利用资源。书中还遵循特定的文档和术语约定，以提高一致性。在后续章节中，预计会详细介绍PowerPC在Linux下的编程技巧、API调用、内存管理、中断处理、异常处理等方面的知识，同时提供实例和调试工具的使用说明。对于那些从事PowerPC/Linux平台开发的工程师来说，这是一本不可或缺的参考资料，它将帮助他们提升开发效率并充分利用PowerPC的潜力。

资源详情

资源推荐

EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)

xvi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

7.5.10.2.1 Virtualization Fault Exceptions <E.HV>........................................................... 7-85

7.5.10.2.2 Page Table Fault Exceptions <E.PT> ................................................................ 7-85

7.5.10.2.3 Instruction Storage Interrupt Settings ................................................................ 7-86

7.5.10.2.4 Data Storage Interrupt Settings.......................................................................... 7-86

7.5.10.3 MAS Register Updates for Exceptions, tlbsx, and tlbre....................................... 7-87

7.5.10.4 LRAT Error Exception and Interrupt <E.HV.LRAT>............................................ 7-91

7.5.11 MMU Configuration Information.............................................................................. 7-91

Chapter 8

Interrupts and Exceptions

8.1 Overview.......................................................................................................................... 8-1

8.2 Interrupt Classes .............................................................................................................. 8-2

8.2.1 Recoverability from Interrupts..................................................................................... 8-2

8.3 Interrupt Registers............................................................................................................ 8-3

8.3.1 Save/Restore Registers ................................................................................................ 8-5

8.3.2 Other Registers that Help Service the Interrupt........................................................... 8-6

8.4 Directed Interrupts <E.HV> ............................................................................................ 8-7

8.5 Exceptions........................................................................................................................ 8-8

8.6 Synchronous and Asynchronous Interrupts ................................................................... 8-10

8.6.1 Requirements for System Reset Generation .............................................................. 8-11

8.7 Interrupt Processing ....................................................................................................... 8-11

8.8 Interrupt Definitions ...................................................................................................... 8-13

8.8.1 Critical Input Interrupt............................................................................................... 8-18

8.8.2 Machine Check, NMI, and Error Report Interrupts................................................... 8-19

8.8.2.1 General Machine Check, Error Report, and NMI Mechanism.............................. 8-19

8.8.2.1.1 Error Detection and Reporting Overview.......................................................... 8-20

8.8.2.1.2 Machine Check and Non-Maskable Interrupts Considerations......................... 8-21

8.8.2.2 NMI Interrupts ....................................................................................................... 8-22

8.8.2.3 Error Report Synchronous Interrupts..................................................................... 8-22

8.8.2.4 Asynchronous Machine Check Interrupts ............................................................. 8-23

8.8.3 Data Storage Interrupt................................................................................................ 8-23

8.8.4 Instruction Storage Interrupt ...................................................................................... 8-27

8.8.5 External Input Interrupt ............................................................................................. 8-30

8.8.5.1 External Proxy <EXP> .......................................................................................... 8-31

8.8.6 Alignment Interrupt ................................................................................................... 8-32

8.8.7 Program Interrupt....................................................................................................... 8-33

8.8.8 Floating-Point Unavailable Interrupt <FP> ............................................................... 8-35

8.8.9 System Call Interrupt ................................................................................................. 8-35

8.8.10 Decrementer Interrupt................................................................................................ 8-36

8.8.11 Fixed-Interval Timer Interrupt ................................................................................... 8-37

EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)

Freescale Semiconductor xvii

Contents

Paragraph

Number Title

Page

Number

8.8.12 Watchdog Timer Interrupt.......................................................................................... 8-38

8.8.13 Data TLB Error Interrupt........................................................................................... 8-41

8.8.14 Instruction TLB Error Interrupt ................................................................................. 8-43

8.8.15 Debug Interrupt.......................................................................................................... 8-44

8.8.16 SPE/Embedded Floating-Point/AltiVec Unavailable Interrupt <SP or V> ............... 8-45

8.8.17 Embedded Floating-Point Data Interrupt <SP.FD, SP.FS, SP.FV> ........................... 8-46

8.8.18 AltiVec Assist Interrupt <V> ..................................................................................... 8-47

8.8.19 Embedded Floating-Point Round Interrupt <SP.FD, SP.FS, SP.FV> ........................ 8-48

8.8.20 Performance Monitor Interrupt <E.PM> ................................................................... 8-49

8.8.21 Processor Doorbell Interrupt <E.PC>........................................................................ 8-50

8.8.22 Processor Doorbell Critical Interrupt <E.PC>........................................................... 8-51

8.8.23 Guest Processor Doorbell Interrupt <E.HV>............................................................. 8-51

8.8.24 Guest Processor Doorbell Critical Interrupt <E.HV>................................................ 8-52

8.8.25 Guest Processor Doorbell Machine Check Interrupt <E.HV> .................................. 8-53

8.8.26 Embedded Hypervisor System Call Interrupt <E.HV> ............................................. 8-54

8.8.27 Embedded Hypervisor Privilege Interrupt <E.HV> .................................................. 8-54

8.8.28 LRAT Error Interrupt <E.HV.LRAT>........................................................................ 8-55

8.9 Partially Executed Instructions ...................................................................................... 8-56

8.10 Interrupt Ordering and Masking .................................................................................... 8-57

8.10.1 Guidelines for System Software ................................................................................ 8-59

8.11 Exception Priorities........................................................................................................8-60

8.12 Processor Signaling (msgsnd and msgclr) <E.PC> ....................................................... 8-64

8.12.1 Sending Messages...................................................................................................... 8-64

8.12.2 Receiving, Filtering, and Accepting Messages.......................................................... 8-66

8.12.3 Message Types and Definitions ................................................................................. 8-67

Chapter 9

Timer Facilities

9.1 Timer Facilities ................................................................................................................ 9-1

9.2 Timer Registers ................................................................................................................ 9-2

9.3 Time Base Operation ....................................................................................................... 9-3

9.3.1 Writing the TB .............................................................................................................9-3

9.3.2 Reading the TB ............................................................................................................ 9-4

9.3.3 Computing Time of Day from the Time Base ............................................................. 9-4

9.3.4 Nonconstant Update Frequency................................................................................... 9-6

9.4 Decrementer Operation.................................................................................................... 9-6

9.5 Fixed-Interval Timer ........................................................................................................ 9-7

9.6 Watchdog Timer...............................................................................................................9-8

9.7 Alternate Time Base....................................................................................................... 9-10

9.8 Freezing the Timer Facilities ......................................................................................... 9-10

EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)

xviii Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

Chapter 10

Debug Facilities

10.1 Debug Facilities Overview ............................................................................................ 10-1

10.2 Internal and External Debug .......................................................................................... 10-1

10.3 Programming Model ...................................................................................................... 10-2

10.3.1 Debug Registers......................................................................................................... 10-2

10.3.2 Debug Instructions..................................................................................................... 10-2

10.3.3 Debug Interrupt.......................................................................................................... 10-2

10.4 Enabling Internal Debug Mode...................................................................................... 10-3

10.5 External Debug Mode.................................................................................................... 10-3

10.6 Dealing with Debug Resources...................................................................................... 10-3

10.6.1 Synchronizing Changes to Debug Facility Registers ................................................ 10-4

10.6.2 Pre-Completion and Post-Completion Interrupts ...................................................... 10-4

10.6.2.1 Synchronous Pre-Completion Debug Interrupts.................................................... 10-4

10.6.2.2 Synchronous Post-Completion Debug Interrupts .................................................. 10-5

10.6.2.3 Asynchronous Debug Interrupts............................................................................ 10-5

10.7 Debug Conditions and Debug Events ............................................................................ 10-5

10.7.1 Suppressing Debug Events in Hypervisor Mode....................................................... 10-7

10.7.2 Instruction Address Compare Debug Event .............................................................. 10-7

10.7.2.1 Instruction Address Compare User/Supervisor Mode ........................................... 10-7

10.7.2.2 Effective/Real Address Mode................................................................................ 10-7

10.7.2.3 Instruction Address Compare Mode...................................................................... 10-7

10.7.2.4 Instruction Address Compare Debug Event Considerations ................................. 10-8

10.7.3 Data Address Compare Debug Event ........................................................................ 10-9

10.7.3.1 Data Address Compare Read/Write Enable........................................................... 10-9

10.7.3.2 Data Address Compare User/Supervisor Mode................................................... 10-10

10.7.3.3 Effective/Real Address Mode.............................................................................. 10-10

10.7.3.4 Data Address Compare Mode.............................................................................. 10-10

10.7.3.5 Data Value Compare Mode.................................................................................. 10-11

10.7.3.6 Data Address Compare Debug Event Considerations ......................................... 10-11

10.7.4 Trap Debug Event .................................................................................................... 10-12

10.7.5 Branch Taken Debug Event ..................................................................................... 10-13

10.7.6 Instruction Complete Debug Event.......................................................................... 10-13

10.7.7 Interrupt Taken Debug Event................................................................................... 10-14

10.7.8 Critical Interrupt Taken Debug Event <E.ED> ....................................................... 10-15

10.7.9 Return Debug Event................................................................................................. 10-15

10.7.10 Critical Interrupt Return Debug Event <E.ED> ...................................................... 10-16

10.7.11 Unconditional Debug Event (UDE)......................................................................... 10-16

10.7.12 DAC and IAC Linking............................................................................................. 10-17

EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)

Freescale Semiconductor xix

Contents

Paragraph

Number Title

Page

Number

Chapter 11

Performance Monitor <E.PM>

11.1 Performance Monitor Overview .................................................................................... 11-1

11.2 Performance Monitor Features ...................................................................................... 11-1

11.3 Performance Monitor Programming Model .................................................................. 11-2

11.3.1 Performance Monitor Registers Overview ................................................................ 11-2

11.3.2 Using PMRs to Control and Access Performance Monitoring.................................. 11-3

11.3.3 Performance Monitor Interrupt Model ...................................................................... 11-4

11.4 Performance Monitor Use Case ..................................................................................... 11-4

11.4.1 Event Counting .......................................................................................................... 11-5

11.4.2 Processor Context Configurability............................................................................. 11-5

11.4.2.1 Enabling the Monitor of Processor States.............................................................. 11-5

11.4.2.2 Specifying Unconditional Counting Modes .......................................................... 11-6

11.4.3 Event Selection .......................................................................................................... 11-6

11.4.4 Chaining Counters ..................................................................................................... 11-6

11.4.5 Thresholds.................................................................................................................. 11-7

Appendix A

Instruction Set Listings

A.1 Instructions Sorted by Mnemonic (Decimal).................................................................. A-2

A.2 Instructions Sorted by Opcodes (Decimal) ................................................................... A-31

A.3 Instructions Sorted by Mnemonic (Binary) .................................................................. A-58

A.4 Instructions Sorted by Opcode (Binary) ....................................................................... A-85

A.5 Instruction Set Sorted by Form (Decimal)...................................................................A-112

Appendix B

Simplified Mnemonics

B.1 Simplified Mnemonics Overview....................................................................................B-1

B.2 Subtract Simplified Mnemonics ......................................................................................B-1

B.2.1 Subtract Immediate ......................................................................................................B-1

B.2.2 Subtract ........................................................................................................................B-2

B.3 Rotate and Shift Simplified Mnemonics..........................................................................B-2

B.3.1 Operations on Words ...................................................................................................B-3

B.3.2 Operations on Double-words .......................................................................................B-3

B.4 Branch Instruction Simplified Mnemonics......................................................................B-4

B.4.1 Key Facts about Simplified Branch Mnemonics .........................................................B-5

B.4.2 Eliminating the BO Operand .......................................................................................B-6

B.4.3 Incorporating the BO Branch Prediction .....................................................................B-7

EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)

xx Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

B.4.4 The BI Operand—CR Bit and Field Representations..................................................B-8

B.4.4.1 BI Operand Instruction Encoding............................................................................B-9

B.4.5 Simplified Mnemonics that Incorporate the BO Operand .........................................B-11

B.4.5.1 Examples that Eliminate the BO Operand.............................................................B-12

B.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates

BO and Replaces BI with crS) ..............................................................................B-15

B.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions:

Examples ...........................................................................................................B-17

B.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions:

Listings ..............................................................................................................B-17

B.5 Compare Word Simplified Mnemonics .........................................................................B-19

B.6 Compare Double-word Simplified Mnemonics.............................................................B-20

B.7 Condition Register Logical Simplified Mnemonics ......................................................B-21

B.8 Trap Instructions Simplified Mnemonics ......................................................................B-21

B.9 Simplified Mnemonics for Accessing SPRs..................................................................B-23

B.10 Recommended Simplified Mnemonics..........................................................................B-24

B.10.1 No-Op (nop) ..............................................................................................................B-24

B.10.2 Load Immediate (li) ...................................................................................................B-24

B.10.3 Load Address (la) ......................................................................................................B-24

B.10.4 Move Register (mr) ...................................................................................................B-25

B.10.5 Complement Register (not) .......................................................................................B-25

B.10.6 Move to Condition Register (mtcr)...........................................................................B-25

B.10.7 Sync (sync) ................................................................................................................B-26

B.10.8 Integer Select (isel) ....................................................................................................B-26

B.10.9 System Call (sc) .........................................................................................................B-26

B.10.10 Wait for Interrupt (wait) ............................................................................................B-26

B.10.11 TLB Invalidate Local Indexed ...................................................................................B-27

Appendix C

Programming Examples

C.1 Synchronization ...............................................................................................................C-1

C.1.1 Synchronization Primitives..........................................................................................C-2

C.1.1.1 Memory Barriers......................................................................................................C-2

C.1.1.2 Fetch and No-op ......................................................................................................C-2

C.1.1.3 Fetch and Store ........................................................................................................C-3

C.1.1.4 Fetch and Add..........................................................................................................C-3

C.1.1.5 Fetch and AND ........................................................................................................C-3

C.1.1.6 Test and Set ..............................................................................................................C-3

C.1.1.7 Compare and Swap ..................................................................................................C-4

C.1.2 Lock Acquisition and Release .....................................................................................C-4

剩余1164页未读，继续阅读

liujixun8268771

粉丝: 0
资源: 2

PowerPC Linux编程指南：EIS支持的e500/e200处理器详解

PowerPC750cl处理器用户手册

PowerPC 汇编与C语言互调的eabi规范

powerpc 选型手册(freescale).pdf

linux配置powerpc-linux-gcc

powerpc750处理器 数据手册

powerpc c语言教程

linux+powerpc+tlb+表+和+uboot+关系

powerpc开发工具

power pc有哪些内核

xilinx引导powerpc

power pc有哪些系列的内核

powerPC与ARM区别

现在嵌入式主流的power pc处理器有哪些

PowerPc 是什么架构

power pc e200是什么

powerpc开发环境搭建过程

powerpc 系统调用向量

powerpc qt

powerPC PC指针

powerpc 网关

最新资源

powerpc750处理器数据手册