Section number Title Page
17.2.3.2 4K+128 flash, 10 bytes metadata, 1024 byte data blocks, separate metadata, assuming
GF(213) for data and GF(214) for metadata..........................................................................736
17.2.4 Data Buffers in System Memory............................................................................................................... 736
17.3 Memory to Memory (Loopback) Operation................................................................................................................. 738
17.4 Programming the BCH/GPMI Interfaces......................................................................................................................739
17.4.1 BCH Encoding for NAND Writes............................................................................................................. 739
17.4.1.1 DMA Structure Code Example..............................................................................................742
17.4.1.2 Using the BCH Encoder.........................................................................................................747
17.4.2 BCH Decoding for NAND Reads..............................................................................................................748
17.4.2.1 DMA Structure Code Example..............................................................................................752
17.4.2.2 Using the Decoder..................................................................................................................755
17.4.3 Interrupts.................................................................................................................................................... 757
17.5 Behavior During Reset..................................................................................................................................................758
17.6 BCH Memory Map/Register Definition....................................................................................................................... 759
17.6.1
Hardware BCH ECC Accelerator Control Register (BCH_CTRLn).........................................................760
17.6.2 Hardware ECC Accelerator Status Register 0 (BCH_STATUS0)............................................................ 763
17.6.3 Hardware ECC Accelerator Mode Register (BCH_MODE)..................................................................... 764
17.6.4 Hardware BCH ECC Loopback Encode Buffer Register (BCH_ENCODEPTR).....................................765
17.6.5 Hardware BCH ECC Loopback Data Buffer Register (BCH_DATAPTR).............................................. 765
17.6.6 Hardware BCH ECC Loopback Metadata Buffer Register (BCH_METAPTR).......................................766
17.6.7 Hardware ECC Accelerator Layout Select Register (BCH_LAYOUTSELECT)..................................... 766
17.6.8 Hardware BCH ECC Flash 0 Layout 0 Register (BCH_FLASH0LAYOUT0).........................................768
17.6.9 Hardware BCH ECC Flash 0 Layout 1 Register (BCH_FLASH0LAYOUT1).........................................770
17.6.10 Hardware BCH ECC Flash 1 Layout 0 Register (BCH_FLASH1LAYOUT0).........................................771
17.6.11 Hardware BCH ECC Flash 1 Layout 1 Register (BCH_FLASH1LAYOUT1).........................................773
17.6.12 Hardware BCH ECC Flash 2 Layout 0 Register (BCH_FLASH2LAYOUT0).........................................774
17.6.13 Hardware BCH ECC Flash 2 Layout 1 Register (BCH_FLASH2LAYOUT1).........................................776
17.6.14 Hardware BCH ECC Flash 3 Layout 0 Register (BCH_FLASH3LAYOUT0).........................................777
17.6.15 Hardware BCH ECC Flash 3 Layout 1 Register (BCH_FLASH3LAYOUT1).........................................779
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 5, 06/2018
20 NXP Semiconductors