DW3000 UWB Transceiver User Guide

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"DW3000用户手册，包含了如何使用、配置和控制DW3000 UWB收发器的详细指南。" DW3000是Decawave公司推出的一款超宽带（UWB）无线通信芯片，适用于高精度定位、物联网（IoT）设备和无线数据传输应用。该手册的目的是帮助用户理解和操作DW3000，确保其在各种应用场景中高效工作。 1. **DW3000介绍** DW3000是一款先进的UWB收发器，设计用于提供精确的距离测量和高速数据传输。它支持低功耗模式，适用于需要长时间工作的设备。 2. **文档概述** 用户手册旨在为用户提供全面的指导，包括DW3000的功能、接口方法、操作状态、电源管理以及数据传输和接收的机制。 3. **DW3000概览** - **简介**: DW3000与前一代产品DW1000相比，可能具有改进的性能和更多的功能，同时保持向后兼容性。 - **接口**: 描述了如何将DW3000与其他硬件组件连接，如微控制器或传感器。 - **操作状态**: DW3000有多种运行状态，包括休眠、活动、发送和接收等，这些状态决定了设备的能耗和响应速度。 - **电源上电复位（POR）**: 指示设备启动时的初始化过程。 - **UWB频道和前导码**: DW3000使用不同的频道和前导码进行信号同步和信道分配。 - **数据调制方案**: 描述了DW3000如何对数据进行编码以便在UWB信号中传输。 - **同步头调制方案**: 解释了同步头的编码方式，用于设备间的帧同步。 - **物理层（PHY）头**: 包含标准和扩展的数据帧长度信息，定义了数据传输的框架结构。 4. **消息传输** - **基本传输**: 基础的发送流程，包括如何设置数据包和触发传输。 - **传输时间戳**: 时间戳用于精确记录数据包的发送时刻，对于计算距离和同步至关重要。 - **延迟传输**: 允许在预定时间之后发送数据，用于调度和队列管理。 - **扩展长度数据帧**: 支持更长的数据负载，以适应大容量数据传输需求。 5. **消息接收** - **物理层接收**: 详述了接收端如何解码和处理接收到的信号。 - **TDOA和PDOA支持**: TDOA（到达时间差）和PDOA（到达相位差）是定位技术，允许通过多站接收来确定设备的位置。 - **延迟接收**: 接收器可以设定延迟接收，提高系统灵活性。 - **双接收缓冲**: 提供两个接收缓冲区，以实现连续接收和处理多个数据包。 - **低功耗嗅探模式**: 在不影响响应能力的同时，降低了设备的功耗，适用于节能应用。该手册详细地涵盖了DW3000的各个方面，从基本的硬件接口到复杂的通信协议，为开发者和工程师提供了全面的参考资料，帮助他们充分利用DW3000的潜力。通过深入学习和实践，用户能够熟练地集成和优化DW3000在各种应用中的表现。

DW3000 User Manual

Version 1.1

Page 16 of 255

A host wishing to validate the CRC of an SPI read transaction, must calculate its own CRC value across the

header bytes it writes and all the data bytes it subsequently reads for the transaction, and then must read

the IC calculated CRC from the SPI_RD_CRC register, and compare it to the host calculated CRC. If these

don’t match then the host has detected an error in the SPI read.

In the event of an SPI read error, the read can just be repeated, except in the unlikely case that the error

changed the read into a write. In that case a write CRC error will be triggered and this can be handled as

before by resetting the DW3000 and reinitialising/reconfiguring it into the desired operating mode.

2.3.1.3.3 The SPI CRC polynomial / implementation

The CRC is 8-bits long, based on the CRC-8-ATM which has generator polynomial:

G(x) = x

+ x

+ x + 1

and has a typical implementation as shown in Figure 6, where the circle operator is an exclusive-OR.

Input

Figure 6: SPI CRC polynomial implementation

In the DW3000 the shift register (r

to r

) is initialised, at the start of each read or write SPI, with the value

specified in the SPICRCINIT register, which by default is all zeros.

Note: The source code of the DW3000 device driver and API [3] includes functions to generate and check the

SPI CRC along with a simple example that demonstrates their use. The maximum SPI rate supported by

DW3000 when the SPI CRC mode is enable is 20 MHz.

Interrupts

The DW3000 can be configured to assert its IRQ pin on the occurrence of one or more status events. The

assertion of the IRQ pin can be used to interrupt the host controller and redirect program flow to handle the

event.

The polarity of the IRQ pin may be configured via the HIRQ_POL bit in the Sub-register 0x0F:24 – Digital

diagnostics test mode control. By default, on power up the IRQ polarity is active high. This is the

recommended polarity to ensure lowest power operation of the DW3000 in SLEEP and DEEPSLEEP device

states. This pin will float in SLEEP and DEEPSLEEP states and may cause spurious interrupts unless pulled low.

The occurrence of a status event in SYS_STATUS register may assert the IRQ pin depending on the setting of

the corresponding bit in the SYS_ENABLE register.

By default, on power-up, the SPIRDY interrupt generating event enable SPIRDY_EN is set to 1 so that the

interrupt enabled.

DW3000 User Manual

Version 1.1

Page 19 of 255

Overview of main operational states

Table 4: Main DW3000 operational states / modes

State Name

State Description

OFF

In the OFF state the DW3000 is completely powered off, with no voltages applied to

any of its input pins. Power consumption = 0 µA. No I/O pins should be driven or

power will leak through the I/O cells.

WAKE_UP

During the WAKE_UP state the AON sequencer starts up all of the primary power and

clock blocks in order to achieve host comms in the INIT_RC state. The device will

automatically transition from the WAKE_UP state to INIT_RC state.

INIT_RC

Lowest power state with SPI access, but limited to 7 MHz. System is clocked off a

divide-by-four of the FAST_RC clock, i.e., the IC runs at approximately 30 MHz.

IDLE_RC

Lowest power state allowing full speed SPI access. The FAST_RC oscillator is used as

the system clock source, i.e., the IC runs at approximately 120 MHz.

IDLE_PLL/IDLE

In the IDLE_PLL state the DW3000 internal clock generator PLL is locked running at its

nominal 125 MHz rate and ready for use but it is gated off to most circuitry to

minimize power consumption. In the IDLE_PLL state SPI communications can operate

at up to 38 MHz, the maximum SPICLK frequency. In the IDLE_PLL state the analog

receive and transmit circuits are powered down.

The external host can control the DW3000 to initiate a transmission or reception and

thus cause the DW3000 to progress into TX or RX state respectively. If a delayed TX or

RX operation is initiated (see section 3.3 – Delayed transmission and 4.3 - Delayed

receive) then the DW3000 will enter the TX_WAIT or RX_WAIT (until the delayed time

has elapsed) and then enter TX or RX state.

SLEEP

In the SLEEP state the IC consumes < 1 µA from the external power supply inputs. All

internal LDOs are turned off. In the SLEEP state the DW3000 internal low power

oscillator is running and is used to clock the sleep counter whose expiry is

programmed to “wake up” the DW3000 and progress into the WAKE_UP state. While

the IC is in the SLEEP state, the external system should avoid applying power to GPIO,

SPICLK or SPIMISO pins as this will cause an increase in the leakage current.

While device is in the SLEEP state the SPI communication is not possible.

Note: prior to entering SLEEP state AINIT2IDLE configuration bit in SEQ_CTRL

state after wake up and the host can then load LDOTUNE_CAL values from OTP prior

to changing into IDLE_PLL state.

DW3000 User Manual

Version 1.1

Page 20 of 255

State Name

State Description

DEEPSLEEP

With the exception of the OFF state, the DEEPSLEEP state is the lowest power state of

the device. In this state the IC consumes < 250 nA from the external power supply

inputs.

In DEEPSLEEP all internal circuitry is powered down with the exception of the always-

on memory which can be used to hold the device configuration for restoration on

wake up

Once in DEEPSLEEP, the DW3000 remains in this state until the occurrence of a wake

up event. This can be either:

1. the SPICSn line pulled low or

2. the WAKEUP line driven high

for the duration quoted in the DW3000 Datasheet [5] (nominally 500 μs).

Once the DW3000 has detected a wake up event it progresses into the WAKE_UP

state. While the IC is in DEEPSLEEP state, the external system should avoid applying

power to GPIO, SPICLK or SPIMISO pins as this will cause an increase in leakage

current.

Note: Asserting the RSTn pin (hardware reset) will also take the device out of

DEEPSLEEP, however device will be fully reset in that case.

While device is in the DEEPSLEEP state the SPI communication is not possible.

See Note: above (in SLEEP state) on clearing of AINIT2IDLE prior to entering

DEEPSLEEP state.

TX_WAIT

This state is very like the IDLE_PLL state except the IC is implementing a delay prior to

transmission, typically aiming to transmit the RMARKER at a specified time. At the

apprioiate moment the TX analog blocks are turned on and the device transitions into

the TX.

RX_WAIT

This state is very like the IDLE_PLL state except the IC is implementing a delay prior to

turning on the receiver. At the apprioiate time the RX analog blocks are turned on

and the device transitions into the RX state.

TX state

In the TX the DW3000 actively transmits a packet (generally containing the contents

of the transmit buffer) on the configured RF channel with the configured transmit

parameters (PRF, data rate, preamble code etc.)

Once the transmission is complete the DW3000, will go back to the IDLE_PLL state,

following which it may enter RX state (e.g. if using wait for response command) or go

to a low-power state depending on the programmed configuration. If the ATX2SLP bit

is set (in SEQ_CTRL) the DW3000 will enter the SLEEP or DEEPSLEEP state

automatically, see “Auto-to-sleep” path in Figure 7 (as long as no host interrupts are

pending).

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