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INTRODUCTION CHAPTER 1
1–5
irrelevant to the MIPS architecture. For example, the MIPS architecture
does not mandate a stack pointer or stack usage; thus, programmers may
be surprised to find that push/pop instructions do not exist directly.
The most notable of these features are summarized here.
Unusual instruction encoding features
•
All instructions are 32-bits long
: as mentioned above. This means, for
example, that it is impossible to incorporate a 32-bit constant into a
single instruction (there would be no instruction bits left to encode
the operation and the registers!). A ‘‘load immediate’’ instruction is
limited to a 16-bit value; a special ‘‘load upper immediate’’ must be
followed by an ‘‘or immediate’’ to put a 32-bit constant value into a
register.
•
Instruction actions must fit the pipeline
: actions can only be carried out
in the designated pipeline phase, and must be complete in one clock.
For example, the register writeback phase provides for just one value
to be stored in the register file, so instructions can only change one
register.
•
3-operand instructions
: arithmetic/logical operations don’t have to
specify memory locations, so there are plenty of instruction bits to
define two independent source and one destination register.
Compilers love 3-operand instructions, which give optimizers more
scope to improve the code which handles complex expressions.
•
32 registers
: the choice of 32 has become universal; compilers like a
large (but not necessarily too large) number of registers, but there is
a cost in context-saving and in encoding the registers to be used by
an instruction. Register $0 always returns zero, to give a compact
encoding of that useful constant.
•
No condition codes
: the MIPS architecture does not provide condition
code flags implicitly set by arithmetical operations. The motivation is
to make sure that execution state is stored in one place – the register
file. Conditional branches (in MIPS) test a single register for sign/zero,
or a pair of registers for equality.
Addressing and memory accesses
•
Memory references are always register loads and stores
: arithmetic on
memory variables upsets the pipeline, so is not done. Memory
references only occur due to explicit load or store instructions. The
large register file allows multiple variables to be “on-chip”
simultaneously.
•
Only one data addressing mode
: all loads and stores define the
memory location with a single base register value modified by a 16-bit
signed displacement. Note that the assembler/compiler tools can use
the $0 register, along with the immediate value, to synthesize
additional addressing modes from this one directly supported mode.
•
Byte-addressed
: the instruction set includes load/store operations
for 8- and 16-bit variables (referred to as
byte
and
halfword
). Partial-
word load instructions come in two flavors – sign-extend and zero-
extend.
•
Loads/stores must be address-aligned
: memory word operations can
only load or store data from a single 4-byte aligned word; halfword
operations must be aligned on half-word addresses. Many CISC
microprocessors will load/store a multi-byte item from any byte
address (although unaligned transfers always take longer).
Techniques to generate code which will handle unaligned data
efficiently will be explained later.
•
Jump instructions
: The smallest op-code field in a MIPS instruction is
6 bits; leaving 26 bits to define the target of a jump. Since all
instructions are 4-byte aligned in memory the two least-significant