TPS65982：USB Type-C PD控制器与高速多路复用器

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"TI的TPS65982是一款集成USB Type-C PD控制器、电源开关和高速多路复用器的芯片，适用于USB Type-C连接器的主机或设备端，支持电源输送协议，并具备插头方向检测功能。" TPS65982是德州仪器(TI)推出的一款专门针对USB Type-C接口设计的高性能控制器，它集成了USB Power Delivery (PD) 控制器、电源开关以及高速多路复用器。该芯片在USB Type-C生态系统中扮演着重要角色，能够处理主机（Host）与设备（Sink）之间的通信和供电管理。 USB PD控制器是TPS65982的核心部分，它实现了USB PD协议的通信，允许在源（Host）和接收器（Sink）之间进行灵活的电压和电流协商，从而提供最高可达20V/5A（100W）的电力传输。该控制器支持Bi-Phase Marked Encoding/Decoding (BMC) 编码解码，确保在CC线上的稳定通信。 TPS65982具有插头插入和方向检测功能，能够自动识别USB Type-C连接器的正反面，确保了用户在连接设备时无需考虑插头的方向性。当连接器检测到电缆插入后，芯片会启动USB PD协议进行电源配置和通信协商。在物理层(PHY)协议层面，TPS65982负责执行USB PD的规范，包括信号的编码、解码和传输。同时，该芯片还集成了电源开关，可以控制VBUS的通断，确保在PD协议协商完成后，按照协商的电压和电流为下游设备供电。此外，TPS65982还包含了一个高速多路复用器，可以切换D+/D-、SBU1/2等线路，以适应不同的USB连接模式，如USB 2.0数据传输、SuperSpeed USB数据传输，以及Sideband Use (SBU) 线路的交替模式操作。这使得TPS65982能够支持多种USB Type-C配置，如DisplayPort、Thunderbolt等。在安全性和保护方面，TPS65982内置了VBUS过流保护、短路保护等功能，确保了系统在异常情况下的稳定性。它还支持Type-C电缆检测，可以识别连接的电缆类型，以适应不同性能的电缆。 TPS65982是一款高度集成的USB Type-C解决方案，适用于需要高效、安全电源管理和通信功能的移动设备、充电器、适配器和其他USB Type-C产品。开发人员可以利用这款芯片简化设计，提高产品的兼容性和可靠性。

TPS65982

SLVSD02A –MARCH 2015–REVISED JUNE 2015

www.ti.com

6.12 Port Data Multiplexer Switching and Timing Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SWD MULTIPLEXER PATH

(1)

= 3.3 V, I

= 20 mA 35 55

On resistance of SWD_DATA/CLK to

SWD_RON_U Ω

C_USB_TP/TN/BP/BN

= 1 V, I

= 20 mA 30 46

On resistance difference between P and N paths of

SWD_ROND_U V

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

SWD_DATA/CLK to C_USB_ TP/TN/BP/BN

= 3.3 V, I

= 20 mA 26 42

SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2 Ω

= = 1 V, I

= 20 mA 24 37

On resistance difference between P and N paths of

SWD_ROND_S V

= 1V to 3.3 V, I

= 20 mA –1.5 1.5 Ω

SWD_DATA/CLK to C_SBU1/2

Time from enable bit with charge

150

pump off

SWD_TON Switch on time from enable of SWD path μs

Time from enable bit at charge

pump steady state

Time from disable bit at charge

SWD_TOFF Switch off time from disable of SWD path 500 ns

pump steady state

SWD_BW 3 dB bandwidth of SWD path C

= 10 pF 200 MHz

DEBUG1/2 MULTIPLEXER PATH

(1)

= 3.3 V, I

= 20 mA 14 26

DB1_RON_U On resistance DEBUG1/2 to C_USB_TP/TN/BP/BN Ω

= 1 V, I

= 20 mA 10 17

On resistance difference between P and N paths of

DB1_ROND_U V

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

DEBUG1/2 to C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 9.5 17

DB1_RON_S On resistance of DEBUG1/2 to C_SBU1/2 Ω

= 1 V, I

= 20 mA 6.5 12

On resistance difference between P and N paths of Debug

DB1_ROND_S V

= 1 V to 3.3 V, I

= 20 mA –0.5 0.5 Ω

path DEBUG1/2 to C_SBU1/2

Time from enable bit with charge

150

pump off

DB1_TON Switch on time from enable of DEBUG path μs

Time from enable bit at charge

pump steady state

Time from disable bit at charge

DB1_TOFF Switch off time from disable of DEBUG path 500 ns

pump steady state

DB1_BW 3dB bandwidth of DEBUG path C

= 10 pF 200 MHz

DEBUG3/4 MULTIPLEXER PATH

(1)

= 3.3 V, I

= 20 mA 14 24

DB3_RON_U On resistance of DEBUG3/4 to C_USB_TP/TN/BP/BN Ω

= 1 V, I

= 20 mA 9 17

On resistance difference between P and N paths of

DB3_ROND_U V

= 1 V to 3.3V, I

= 20 mA –1.5 1.5 Ω

DEBUG3/4 to C_USB_ TP/TN/BP/BN

= 3.3 V, I

= 20 mA 9.5 18

DB3_RON_S On resistance of DEBUG3/4 to C_SBU1/2 Ω

= 1 V, I

= 20 mA 6.5 12

On resistance difference between P and N paths of

DB3_ROND_S V

= 1 V to 3.3 V, I

= 20 mA –0.15 0.15 Ω

DEBUG3/4 to C_SBU1/2

Time from enable bit with charge

150

pump off

DB3_TON Switch on time from enable of DEBUG3/4 path μs

Time from enable bit at charge

pump steady state

Time from disable bit at charge

DB3_TOFF Switch off time from disable of DEBUG3/4 path 500 ns

pump steady state

DB3_BW 3dB bandwidth of DEBUG3/4 path C

= 10 pF 200 MHz

(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum

difference between the two switches in a pair. ROND does not add to RON.

Product Folder Links: TPS65982

TPS65982

www.ti.com

SLVSD02A –MARCH 2015–REVISED JUNE 2015

Port Data Multiplexer Switching and Timing Characteristics (continued)

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT

LSX_R2P/P2R MULTIPLEXER PATH

(1)

= 3.3 V, I

= 20 mA 8.5 17

LSX_RON On resistance of LSX_P2R/R2P to C_SBU1/2 Ω

= 1 V, I

= 20 mA 5.5 11

On resistance difference between P and N paths of LSX

LSX_ROND V

= 1 V to 3.3 V, I

= 20 mA –0.3 0.3 Ω

path

Time from enable bit with charge

150

pump off

LSX_TON Switch on time from enable of LSX path μs

Time from enable bit at charge

pump steady state

Time from disable bit at charge

LSX_TOFF Switch off time from disable of LSX path 500 ns

pump steady state

LSX_BW 3dB bandwidth of LSX path C

= 10 pF 200 MHz

AUX MULTIPLEXER PATH

(1)

= 3.3 V, I

= 20 mA 3.5 7

AUX_RON On resistance of AUX_P/N to C_SBU1/2 Ω

= 1 V, I

= 20 mA 2.5 5

On resistance difference between P and N paths of

AUX_ROND V

= 1 V to 3.3 V, I

= 20 mA –0.25 0.25 Ω

AUX_P/N to C_SBU1/2

Time from enable bit with charge

150

pump off

AUX_TON Switch on time from enable of AUX_P/N to C_SBU1/2 μs

Time from enable bit at charge

pump steady state

Time from disable bit at charge

AUX_TOFF Switch off time from disable of AUX_P/N to C_SBU1/2 500 ns

pump steady state

AUX_BW 3dB bandwidth of AUX_P/N to C_SBU1/2 path C

= 10 pF 200 MHz

UART MULTIPLEXER PATH (2

Stage Only)

(1)(2)

On resistance of UART buffers to C_USB_TP/TN/BP/BN or

UART_RON V

= 3.3 V, I

= 20 mA 3.1 12 Ω

C_SBU1/2

Time from enable bit with charge

150

pump off

Switch on time from enable of UART buffer

UART_TON µs

C_USB_TP/TN/BP/BN or C_SBU1/2 path

Time from enable bit at charge

pump steady state

Time from disable bit at charge

UART_TOFF Switch off time from disable of UART buffer path 500 ns

pump steady state

UART_BW 3dB bandwidth of UART buffer path C

= 10 pF 200 MHz

USB_RP MULTIPLEXER PATH

(1)(3)

= 3 V, I

= 20 mA 4.5 10

USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN Ω

= 400 mV, I

= 20 mA 3 7

On resistance difference between P and N paths of

USB_ROND V

= 0.4 V to 3 V, I

= 20 mA –0.15 0.15 Ω

USB_RP to C_USB_TP/TN/BP/BN

Time from enable bit with charge

150

pump off

USB_TON Switch on time from enable of USB USB_RP path µs

Time from enable bit at charge

pump steady state

Time from disable bit at charge

USB_TOFF Switch off time from disable of USB_RP path 500 ns

pump steady state

USB_BW 3dB bandwidth of USB_RP path C

= 10 pF 850 MHz

= 50 Ω, V

= 800 mV, f = 240

USB_ISO Off Isolation of USB_RP path –19 dB

MHz

USB_XTLK Channel to Channel crosstalk of USB_RP path R

= 50 Ω, f = 240 MHz –26 dB

C_SBU1/2 OUTPUT

R_SBU_OPEN Resistance of the open C_SBU1/2 paths V

= 0 V to LDO_3V3 1 MΩ

R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths V

= 0 V to LDO_3V3 1 MΩ

(2) The UART switch path connects from the UART buffers to the port pins. See Input/Output (I/O) Requirements and Characteristics for

buffer specifications.

(3) See Port Data Multiplexer USB Endpoint Requirements and Characteristics for the USB_EP specifications.

Product Folder Links: TPS65982

TPS65982

SLVSD02A –MARCH 2015–REVISED JUNE 2015

www.ti.com

6.13 Port Data Multiplexer Clamp Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT

VCLMP_IND Clamp Voltage triggering indicator to Digital Core 3.8 3.95 4.1 V

ICLMP_IND Clamp Current at VCLMP_IND 10 250 μA

Time from clamp current crossing ICLMP_IND to

TCLMP_PRT

(1)

I ≥ ICLMP_IND rising 0 4 μs

interrupt signal assertion

V = LDO_3V3 250 nA

ICLMP USB_EP and USB_RP Port Clamp Current

V = VCLMP_IND + 500 mV 3.5 15 mA

(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time

may be longer.

6.14 Port Data Multiplexer SBU Detection Requirements

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH_PORT Port switch detect input high voltage LDO_3V3 = 3.3 V 2.0 v

VIL_PORT Port switch detect input low voltage LDO_3V3 = 3.3 V 0.8 V

6.15 Port Data Multiplexer Signal Monitoring Pull-Up and Pull-Down Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RPU05 500-Ω pull-up/down resistance LDO_3V3 = 3.3 V 350 500 650 Ω

RTPU5 5-kΩ pull-up/down resistance LDO_3V3 = 3.3 V 3.5 5 6.5 kΩ

RPU100 100-kΩ pull-up/down resistance LDO_3V3 = 3.3 V 70 100 130 kΩ

6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Transmitter

(1)

T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns

T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns

T_RRM_EP Rise/Fall time matching Low-speed (1.5 Mbps) data rate only –20% 25%

V_XOVER_EP Output crossover voltage 1.3 2 V

Source resistance of driver including 2nd Stage Port

RS_EP 34 Ω

Data Multiplexer

Differential Receiver

(1)

VOS_DIFF_EP Input offset –100 100 mV

VIN_CM_EP Common Mode Range 0.8 2.5 V

RPU_EP D- Bias Resistance Receiving 1.425 1.575 kΩ

Single Ended Receiver

(1)

VTH_SE_EP Single ended threshold Signal rising/falling 0.8 2 V

VHYS_SE_EP Single ended threshold hysteresis Signal falling 200 mV

(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for

VIN_3V3 ≥ 3.135 V

Product Folder Links: TPS65982

TPS65982

www.ti.com

SLVSD02A –MARCH 2015–REVISED JUNE 2015

6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Data Contact Detect

IDP_SRC DCD Source Current LDO_3V3 = 3.3 V 7 10 13 μA

RDM_DWN DCD pull-down resistance 14.25 20 24.8 kΩ

VC_USB_TP/BP ≥

VLGC_HI Threshold for no connection VLGC_HILDO_3V3 = 3.3 V 2 V

LDO_3V3 = 3.3 V

VC_USB_TP/BP ≤ VLGC_LO

VLGC_LO Threshold for connection 0.8 V

LDO_3V3 = 3.3 V

Primary and Secondary Detect

VDX_SRC Source voltage 0.55 0.6 0.65 V

VDX_RSRC Total series resistance due to Port Data Multiplexer VDX_SRC = 0.65 V 65 Ω

VDX_ILIM VDX_SRC current limit 250 400 μA

IDX_SNK Sink Current VC_USB_TN/BN ≥ 250 mV 25 75 125 μA

6.18 Analog-to-Digital Converter (ADC) Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT

RES_ADC ADC Resolution 10 bits

F_ADC ADC clock frequency 1.477 1.5 1.523 MHz

T_ENA ADC enable time 42.14 43 43.86 μs

T_SAMPLEA ADC input sample time 10.5 10.67 10.9 μs

T_CONVERTA ADC conversion time 7.88 8 8.12 μs

T_INTA ADC interrupt time 1.31 1.33 1.35 μs

LSB Least Significant Bit 1.152 1.17 1.188 mV

DNL Differential Non-linearity –0.65 0.65 LSB

INL Integral Non-linearity –1.2 1.2 LSB

Gain Error (divider) –1.5% 1.5%

GAIN_ERR

Gain Error (no divider) –1 1

VOS_ERR Buffer Offset Error –10 10 mV

THERM_ACC Thermal Sense Accuracy –8 8 °C

THERM_GAIN Thermal slope 3.095 mV/°C

THERM_V0 Zero Degree Voltage 0.823 V

6.19 Input/Output (I/O) Requirements and Characteristics

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SPI

SPI_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V

SPI_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V

SPI_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V

SPI_ILKG Leakage Current Output is Hi-Z, V

= 0 to LDO_3V3 –1 1 μA

SPI Output High Voltage I

= –8 mA, LDO_3V3=3.3 V 2.9 V

SPI_VOH

= –15 mA, LDO_3V3=3.3 V 2.5

SPI Output Low Voltage I

= 10 mA 0.4 V

SPI_VOL

= 20 mA 0.8

Product Folder Links: TPS65982

TPS65982

SLVSD02A –MARCH 2015–REVISED JUNE 2015

www.ti.com

Input/Output (I/O) Requirements and Characteristics (continued)

Recommended operating conditions; T

= –10 to 85 °C unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SWDIO

SWDIO_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V

SWDIO_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V

SWDIO_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V

SWDIO_ILKG Leakage Current Output is Hi-Z, V

= 0 to LDO_3V3 –1 1 μA

Output High Voltage I

= –8 mA, LDO_3V3 = 3.3 V 2.9 V

SWDIO_VOH

= –15 mA, LDO_3V3 = 3.3 V 2.5

Output Low Voltage I

= 10 mA 0.4 V

SWDIO_VOL

= 20 mA 0.8

SWDIO_RPU Pull-up Resistance 2.8 4 5.2 kΩ

SWDIO_TOS SWDIO Output skew to falling edge SWDCLK –5 5 ns

Input Setup time required between SWDIO and rising 6 ns

SWDIO_TIS

edge of SWCLK

Input Hold time required between SWDIO and rising edge 1 ns

SWDIO_TIH

of SWCLK

SWDCLK

SWDCL_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V

SWDCL_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V

SWDCL_THI SWDIOCLK HIGH period 0.05 500 μs

SWDCL_TLO SWDIOCLK LOW period 0.05 500 μs

SWDCL_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V

SWDCL_RPU Pull-up Resistance 2.8 4 5.2 kΩ

GPIO, MRESET, RESETZ, BUSPOWERZ

High Level Input Voltage LDO_3V3 = 3.3 V 2 V

GPIO_VIH

VDDDIO = 1.8 V 1.25

LDO_3V3 = 3.3 V 0.8

GPIO_VIL Low Input Voltage V

VDDIO = 1.8 V 0.63

LDO_3V3 = 3.3 V 0.2

GPIO_HYS Input Hysteresis Voltage V

VDDIO = 1.8 V 0.09

GPIO_ILKG I/O Leakage Current INPU = 0 V to VDD –1 1 μA

GPIO_RPU Pull-up Resistance pull-up enabled 50 100 150 kΩ

GPIO_RPD Pull-down Resistance pull-down enabled 50 100 150 kΩ

GPIO_DG Digital input path de-glitch 20 ns

IO = –2 mA, LDO_3V3 = 3.3 V 2.9

GPIO_VOH GPIO Output High Voltage V

IO = –2 mA, VDDIO = 1.8 V 1.35

IO = 2 mA, LDO_3V3 = 3.3 V 0.4

GPIO_VOL GPIO Output Low Voltage V

IO = 2 mA, VDDIO = 1.8 V 0.45

UART_RX/TX, LSX_P2R/R2P

LDO_3V3 = 3.3 V 2

UARTRX_VIH High Level Input Voltage V

VDDDIO = 1.8 V 1.25

LDO_3V3 = 3.3 V 0.8

UARTRX_VIL Low Input Voltage V

VDDIO = 1.8 V 0.63

LDO_3V3 = 3.3 V 0.2

UARTRX_HYS Input Hysteresis Voltage V

VDDIO = 1.8 V 0.09

= –2 mA, LDO_3V3 = 3.3 V 2.9

UARTTX_VOH GPIO Output High Voltage V

= –2 mA, VDDIO = 1.8 V 1.35

= 2 mA, LDO_3V3 = 3.3 V 0.4

UARTTX_VOL GPIO Output Low Voltage V

= 2 mA, VDDIO = 1.8 V 0.45

UARTTX_RO Output impedance, TX channel LDO_3V3 = 3.3 V 35 70 115 Ω

UARTTX_TRTF Rise and fall time, TX channel 10%–90%, C

= 20 pF 1 40 ns

UART_FMAX Maximum UART baud rate 1.1 Mbps

Product Folder Links: TPS65982

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