JESD251C 2022：扩展串行外设接口(xSPI)标准详解

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"JESD251C是JEDEC固态技术协会发布的一份标准文档，标题为2022 EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES，主要关注扩展串行外设接口（xSPI）在非易失性存储器设备中的应用。该标准的最新版本为JESD251C，是对JESD251B的修订版，发布于2022年5月。" JESD251C标准详细介绍了用于非易失性存储器设备的扩展串行外围接口（xSPI），这是一种专为提高数据传输效率和兼容性而设计的通信协议。xSPI是对传统SPI（串行外设接口）的扩展，旨在满足现代高速、高密度存储器的需求。在xSPI中，"Expanded"一词意味着它增加了对更大带宽、更复杂功能和更多设备支持的需求。此标准涵盖了xSPI的多个方面，包括但不限于： 1. **协议规范**：定义了xSPI的时序和信号特性，例如时钟极性和相位、数据帧格式、命令和地址的传输方式等，确保不同制造商的设备间可以无缝通信。 2. **数据传输速率**：xSPI支持高速数据传输，适应高速非易失性存储器如闪存和EEPROM的需求，提高了系统性能。 3. **多芯片选择**：允许连接多个xSPI设备，通过菊花链或并行配置，增强了系统灵活性和扩展性。 4. **错误检测与纠正**：提供了错误检测和校正机制，确保数据的可靠传输，这对于数据安全性至关重要的非易失性存储器尤为重要。 5. **电源管理**：考虑了低功耗操作，适合电池供电和能源敏感的应用。 6. **兼容性**：保持与现有SPI标准的兼容性，使得已有SPI系统的升级更为平滑。 7. **标准化**：JEDEC标准的采用旨在促进业界统一，减少制造商和消费者之间的误解，提高产品互换性，并简化购买过程。 8. **专利声明**：尽管标准的制定不考虑可能涉及的专利问题，但JEDEC不承担任何对专利持有者的责任，这意味着实施该标准的公司需要自行解决可能的专利冲突。 JESD251C标准为非易失性存储器设备提供了一套全面的xSPI接口规范，旨在优化数据传输效率，提升系统性能，同时保证兼容性和互操作性。这份文档对于设计使用非易失性存储器的硬件工程师、固件开发者以及相关行业的专业人士来说，具有重要的参考价值。

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JEDEC Standard No. 251C

Page 4

3.1 Acronyms

DDR

Double Data Rate. Data is transferred on each edge of a related clock.

Gigabyte: 1,073,741,824 or 2

bytes.

I/O or IO

Input or Output – A signal port that may receive or drive voltage levels to communicate

with other devices.

Kilobyte: 1024 or 2

bytes.

Megabyte: 1,048,576 or 2

bytes

MB/s

Megabytes per second

MSb, LSb

Most Significant Bit or Least Significant Bit

MT/s

Mega Transfers per second

NVM

Non-Volatile Memory

Unit Interval; It is one bit nominal time. For example, UI=5 ns at 200 MHz SDR, UI =

2.5 ns for 200 MHz DDR.

xSPI

eXtended Serial Peripheral Interface

3.2 Conventions

This standard follows some conventions used in other JEDEC documents.

A binary number is represented in this standard by any sequence of digits consisting of only the Western-

Arabic numerals 0 and 1 immediately followed by a lower-case b (e.g., 0101b). Spaces may be included

in binary number representations to increase readability or delineate field boundaries (e.g., 0 0101 1010b).

A hexadecimal number is represented in this standard by any sequence of digits consisting of only the

Western-Arabic numerals 0 through 9 and/or the upper-case English letters A through F

immediately followed by a lower-case h (e.g., FA23h). Spaces may be included in hexadecimal number

representations to increase readability or delineate field boundaries (e.g., B FD8C FA23h).

A decimal number is represented in this standard by any sequence of digits consisting of only

the Western-Arabic numerals 0 through 9 not immediately followed by a lower-case b or lower-case h

(e.g., 25).

A range of numeric values is represented in this standard in the form "a to z", where a is the first value

included in the range, all values between a and z are included in the range, and z is the last value included

in the range (e.g., the representation "0h to 3h" includes the values 0h, 1h, 2h, and 3h).

Other conventions used in this document:

Signals that are considered active when LOW have signal names that end with the hash / pound special

character (i.e., have a suffix of #).

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JEDEC

JEDEC Standard No. 251C

Page 5

3.3 Keywords

Several keywords are used to differentiate levels of requirements and options, as follow:

Can - A keyword used for statements of possibility and capability, whether material, physical, or causal

(can equals is able to).

Expected - A keyword used to describe the behavior of the hardware or software in the design models

assumed by this standard. Other hardware and software design models may also be implemented.

Ignored - A keyword that describes bits, bytes, or fields whose values are not checked by the recipient.

Mandatory - A keyword that indicates items required to be implemented as defined by this standard.

May - A keyword that indicates a course of action permissible within the limits of the standard

(may equals is permitted).

Must - The use of the word must is deprecated and shall not be used when stating mandatory

requirements; must is used only to describe unavoidable situations.

Obsolete - A keyword indicating that an item was defined in prior standards but has been removed from

this standard.

Optional - A keyword that describes features which are not required to be implemented by this standard.

However, if any optional feature defined by the standard is implemented, it shall be implemented

as defined by the standard.

Preferred – A keyword used to identify a feature option which is the preferred option to implement for

compliance with anticipated future revisions of this standard.

Reserved - A keyword used to describe objects—bits, bytes, and fields—or the code values assigned to

these objects in cases where either the object or the code value is set aside for future

standardization.

Usage and interpretation may be specified by future extensions to this or other standards. A

reserved object shall be zeroed or, upon development of a future standard, set to a value

specified by such a standard. The recipient of a reserved object shall not check its value. The recipient

of a defined object shall check its value and reject reserved code values.

Shall - A keyword that indicates a mandatory requirement strictly to be followed in order to conform to

the standard and from which no deviation is permitted (“shall” equals “is required to”). Designers are

required to implement all such mandatory requirements to assure interoperability with other products

conforming to this standard.

Should - A keyword used to indicate that among several possibilities one is recommended as particularly

suitable, without mentioning or excluding others; or that a certain course of action is preferred but not

necessarily required; or that (in the negative form) a certain course of action is deprecated but

not prohibited (“should” equals “is recommended that”).

Will - The use of the word will is deprecated and shall not be used when stating mandatory requirements;

will is only used in statements of fact.

3.4 Abbreviations

etc.: And so forth (Latin: et cetera)

e.g.: For example (Latin: exempli gratia)

i.e.: That is (Latin: id est)

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JEDEC

JEDEC Standard No. 251C

Page 7

5 xSPI Overview

5.1 xSPI Performance Enhancements

Serial interface performance can be enhanced by increasing the basic clock rate, adding source

synchronous clocking, using Double Data Rate (DDR), or by adding parallel data (IO) lines. xSPI allows

all four methods.

Higher clock rates with accurate information transfer are possible by using a separate clock signal for

each direction of information transfer. This is known as source synchronous clocking; providing a timing

reference (clock / strobe) from the source of information, with minimum skew relative to the related

information (data). This enables accurate timing of information capture at the destination device as the

period of valid information decreases at higher clock rates.

DDR can be used to double performance by relating information transfers to both rising and falling edges

of the timing reference.

Up to 8 parallel data (IO) lines are used in xSPI to further increase system performance by transferring

more parallel bits in each clock cycle.

5.2 xSPI Topology and Signal Descriptions

xSPI has a single controller, multiple target bus topology with source synchronous clocking.

Each target device is selected by a separate LOW active Chip Select (CS#) signal from the controller

device.

A clock (CK) signal from the controller to all target devices provides a timing reference for interface

operations. The clock is the timing reference for information transfer on the IO signals from the

controller to the selected target. The clock is also a timing reference for interface operations within the

controller and target interface logic, such as the counting of access latency time. The clock may optionally

be provided by the controller as a differential clock using two signals (CK and CK#). The remaining text

and block diagrams in this standard may only describe one clock (CK) signal for simplicity but, where

ever CK is described or illustrated, a differential pair of CK, CK# may be used. Some xSPI compliant

target devices require a differential clock. A differential clock reduces clock duty cycle distortion and

effectively doubles the clock slew rate, providing improved timing margins for target devices using a

differential clock.

The IO signals provide a bidirectional, variable width path, for information transfer between the controller

and selected target. Different targets on the same bus may use a different IO width for information

transfer.

The Data Strobe (DS) signal provides a timing reference for information transfer on the IO signals from

the target to the controller. DS is an output signal from the xSPI target device that is aligned with the

edges of output data and is used by the controller interface to optimize high frequency read data capture.

DS may optionally be used as a signal from the target to the controller, to indicate the duration of initial

access latency or, as a signal from the controller to the target, to indicate write data masking.

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JEDEC

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