OIF-SFI5-02.0
Serdes Framer Interface Level 5 Phase 2 (SFI-5.2):
Implementation Agreement for 40Gb/s Interface for Physical Layer Devices.
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5 Introduction
The typical line interface of a communications system with 40Gb/s optical links is
expected to consist of three separate devices; an optical module containing a
Serdes component, a forward error correction (FEC) processor and a Framer.
The interconnection between these devices will be electrical where the maximum
data rate per signal is less than the optical data rate. Thus, a multi-bit bus is
required. It is desirable for the protocol of this bus to comply with the following
objectives and requirements:
1. Support up to 44.4Gb/s bi-directional Aggregate data throughput such
as SONET OC-768 [ 2], SDH STM-256 [ 3], OTN OTU3 [ 4] and other
systems operating at a payload data rate in the 40Gb/s range, and
including up to 11% FEC overhead.
2. The interface can be used for point-to-point connection between
Framer and FEC processor, Framer and Serdes, FEC processor and
Serdes. Requirements for electrical parameters and control are the
same between the different components.
3. The interface is intended to handle any format of data, which has been
randomized, e.g. by a scrambler.
4. Capable of driving at least 8” of FR4 interconnect with one connector
5. Interface should be capable of operating indefinitely, without losing
sync.
6. Support both in-band and out-of-band Forward Error Correction (FEC).
A flexible clocking arrangement accounts for the additional FEC
overhead.
7. The interface is independent of the type of optics – serial, CWDM or
parallel, SMF or MMF.
8. Support of skew compensation over the signals comprising the
interface bus. The Deskew algorithm and the skew optimized
transmission used should minimize the complexity of the Serdes
component.
9. Support of simple and robust clock and data recovery of the signals
comprising the interface bus.
10. The interface includes independent status monitoring and supports
received loss of signal detection.
11. Receive timing reference operates continuously, independent of link
status.
12. The receive side of the interface will tolerate being driven while
powered down without damage.
13. The interface includes data path link verification for component
qualification and system integration test purposes.
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