没有合适的资源?快使用搜索试试~ 我知道了~
首页k4b8g1646d-myk0.pdf
k4b8g1646d-myk0.pdf
需积分: 0 15 下载量 8 浏览量
更新于2023-03-03
评论
收藏 1.93MB PDF 举报
k4b8g1646d-myk0数据手册。 不要积分,如果哪天系统自动设置了积分,联系我重新上传。 不要积分,如果哪天系统自动设置了积分,联系我重新上传。
资源详情
资源评论
资源推荐
- 1 -
K4B8G1646D
Rev. 0.9, Jan. 2016
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2016 Samsung Electronics Co., Ltd. All rights reserved.
DDP 8Gb D-die DDR3L SDRAM
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
1.35V
- 2 -
K4B8G1646D datasheet DDP DDR3L SDRAM
Rev. 0.9
Revision History
Revision No. History Draft Date Remark Editor
0.9 - First SPEC release 13th Jan. 2016 - J.Y.Lee
- 3 -
K4B8G1646D datasheet DDP DDR3L SDRAM
Rev. 0.9
Table Of Contents
DDP 8Gb D-die DDR3L SDRAM
1. Ordering Information .....................................................................................................................................................5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing..................................................................................................6
3.1 x16 DDP Package Pinout (Top view) : 96ball FBGA Package................................................................................ 6
3.2 Stacked / Dual - die DDR3 SDRAM x16 Ballout...................................................................................................... 7
3.3 FBGA Package Dimension (x16)............................................................................................................................. 8
4. Input/Output Functional Description..............................................................................................................................9
5. DDR3 SDRAM Addressing ........................................................................................................................................... 10
6. Absolute Maximum Ratings ..........................................................................................................................................11
6.1 Absolute Maximum DC Ratings............................................................................................................................... 11
6.2 DRAM Component Operating Temperature Range ................................................................................................ 11
7. AC & DC Operating Conditions.....................................................................................................................................11
7.1 Recommended DC operating Conditions ................................................................................................................ 11
8. AC & DC Input Measurement Levels ............................................................................................................................12
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12
8.2 VREF Tolerances .................................................................................................................................................... 14
8.3 AC & DC Logic Input Levels for Differential Signals................................................................................................ 15
8.3.1. Differential signals definition ............................................................................................................................ 15
8.3.2. Differential swing requirement for clock (CK - CK
) and strobe (DQS - DQS) .................................................. 15
8.3.3. Single-ended requirements for differential signals ........................................................................................... 16
8.4 Differential Input Cross Point Voltage...................................................................................................................... 18
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 19
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 19
9. AC & DC Output Measurement Levels .........................................................................................................................19
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 19
9.2 Differential AC & DC Output Levels......................................................................................................................... 19
9.3 Single-ended Output Slew Rate .............................................................................................................................. 20
9.4 Differential Output Slew Rate .................................................................................................................................. 21
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 21
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 22
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 22
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 23
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 24
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 25
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 26
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 27
9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 29
9.9 ODT Timing Definitions ........................................................................................................................................... 30
9.9.1. Test Load for ODT Timings.............................................................................................................................. 30
9.9.2. ODT Timing Definitions .................................................................................................................................... 30
10. IDD Current Measure Method.....................................................................................................................................33
10.1 IDD Measurement Conditions ............................................................................................................................... 33
11. DDP 8Gb DDR3 SDRAM D-die IDD Specification Table............................................................................................ 42
12. Input/Output Capacitance ........................................................................................................................................... 43
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 .........................................................
.............44
13.1 Clock Specification ................................................................................................................................................ 44
13.1.1. Definition for tCK(avg).................................................................................................................................... 44
13.1.2. Definition for tCK(abs).................................................................................................................................... 44
13.1.3. Definition for tCH(avg) and tCL(avg).............................................................................................................. 44
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 44
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 44
13.1.6. Definition for tERR(nper)................................................................................................................................ 44
13.2 Refresh Parameters by Device Density................................................................................................................. 45
- 4 -
K4B8G1646D datasheet DDP DDR3L SDRAM
Rev. 0.9
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 45
13.3.1. Speed Bin Table Notes .................................................................................................................................. 49
14. Timing Parameters by Speed Grade ..........................................................................................................................50
14.1 Jitter Notes ............................................................................................................................................................ 54
14.2 Timing Parameter Notes........................................................................................................................................ 55
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 56
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 65
- 5 -
K4B8G1646D datasheet DDP DDR3L SDRAM
Rev. 0.9
1. Ordering Information
[ Table 1 ] Samsung DDP 8Gb DDR3L D-die ordering information table
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. 13th digit stands for below.
"Y" : Commercial temp
"M" : Industrial temp
3. Backward compatible to DDR3-1600(11-11-11)
2. Key Features
[ Table 2 ] DDP 8Gb DDR3 D-die Speed bins
Organization
DDR3L-1600 (11-11-11)
DDR3L-1866 (13-13-13)
3
Package
512Mx16 K4B8G1646D-MYK0 K4B8G1646D-MYMA 96 FBGA
512Mx16 K4B8G1646D-MMK0 K4B8G1646D-MMMA 96 FBGA
Speed
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Unit
6-6-6 7-7-7 9-9-9 11-11-11 13-13-13
tCK(min) 2.5 1.875 1.5 1.25 1.071 ns
CAS Latency 6 7 9 11 13 nCK
tRCD(min) 15 13.125 13.5 13.75 13.91 ns
tRP(min) 15 13.125 13.5 13.75 13.91 ns
tRAS(min) 37.5 37.5 36 35 34 ns
tRC(min) 52.5 50.625 49.5 48.75 47.91 ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
•V
DDQ
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin,
933MHz f
CK
for 1866Mb/sec/pin,
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9(DDR3-1866)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85C, 3.9us at
85C < T
CASE
< 95 C
• Asynchronous Reset
• Support Industrial Temp ( -40~95C)
- tREFI 7.8us at -40C <
TCASE < 85C
- tREFI 3.9us at 85C < TCASE <
95C
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The DDP 8Gb DDR3 SDRAM D-die is organized as a 64Mbit x 16 I/Os x
8banks device. This synchronous device achieves high speed double-data-
rate transfer rates of up to 1866Mb/sec/pin (DDR3-1866) for general appli-
cations.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK
falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS
) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS
/CAS multiplexing style. The DDR3 device operates
with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply
and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V). .
The DDP 8Gb DDR3 D-die device is available in 96ball FBGAs(x16).
NOTE :
1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing Dia-
gram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
剩余71页未读,继续阅读
QQ-2858498411
- 粉丝: 7
- 资源: 19
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- zigbee-cluster-library-specification
- JSBSim Reference Manual
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论0