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Audio Codec ‘97规范
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This specification defines the Audio Codec ‘97 (AC ‘97) Architecture and Digital Interface (AC-link) specifically designed for implementing audio and modem I/O functionality in mainstream PC systems. This specification does not explicitly define the companion AC ‘97 Digital Controller component (sometimes referred to or abbreviated as DC ‘97), which typically varies in features and implementation, but is AC ‘97 compliant with this specification.
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Audio Codec ‘97
Revision 2.3 Revision 1.0
April, 2002
AC ‘97 Component Specification Revision 2.3 Rev 1.0
2
NOTICES
Intel Corporation assumes no responsibility for errors or omissions in the guide. Nor does Intel make any
commitment to update the information contained herein.
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR
INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO
IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. INTEL DOES
NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT
INFRINGE SUCH RIGHTS.
LICENSING
A royalty-free, limited license is available to any interested party who wishes to make use
of this Audio Codec '97 specification. Please contact Intel at audio97@intel.com for
specific Audio Codec '97 licensing terms.
Copyright 2002, Intel Corporation. All Rights Reserved.
** Other names and brands may be claimed as the property of others.
AC ‘97 Component Specification Revision 2.3 Rev 1.0
3
TABLE OF CONTENTS
1. Introduction and Overview.................................................................................................................................9
1.1 AUDIO CODEC FEATURE LIST.........................................................................................................................9
1.2 MODEM CODEC FEATURE LIST.......................................................................................................................9
1.3 AC ‘97 CODEC BLOCK DIAGRAM.................................................................................................................10
1.4 INTEGRATING AC ‘97 INTO THE SYSTEM......................................................................................................11
1.5 DRIVER SUPPORT FOR AC ‘97 CONTROLLER/CODEC INTEROPERABILITY ....................................................12
22. Package, Pinout, and Signal Descriptions........................................................................................................13
2.1 48-PIN QFP PACKAGE ...................................................................................................................................13
2.2 PINOUT .........................................................................................................................................................14
2.3 SIGNAL DESCRIPTIONS .................................................................................................................................15
2.3.1 Power and Ground ..............................................................................................................................15
2.3.2 AC-link and Clocking...........................................................................................................................15
2.3.3 Digital I/O............................................................................................................................................15
2.3.3.1 S/PDIF transmitter pin assignment................................................................................................................... 16
2.3.4 Analog I/O ...........................................................................................................................................16
2.3.5 Filter/References..................................................................................................................................18
3. Controller, Codec, and AC-link........................................................................................................................19
3.1 AC-LINK PHYSICAL INTERFACE....................................................................................................................19
3.2 CONTROLLER TO SINGLE CODEC ..................................................................................................................19
3.3 CONTROLLER TO MULTIPLE CODECS ...........................................................................................................21
3.3.1 Primary Codec Addressing..................................................................................................................22
3.3.2 Secondary Codec Addressing ..............................................................................................................22
3.3.3 Codec ID Strapping .............................................................................................................................22
3.4 CLOCKING FOR MULTIPLE CODEC IMPLEMENTATIONS.................................................................................23
3.4.1 Primary AC, MC, or AMC Codec........................................................................................................23
3.4.2 Secondary AC Codec ...........................................................................................................................23
3.4.3 Secondary MC Codec ..........................................................................................................................23
3.4.3.1 Special AC + MC considerations ..................................................................................................................... 23
3.5 AC-LINK POWER MANAGEMENT ..................................................................................................................24
3.5.1 Powering down the AC-link.................................................................................................................24
3.5.2 Waking up the AC-link.........................................................................................................................24
3.5.2.1 Controller Initiates Wake-up............................................................................................................................ 24
3.5.2.2 Codec Initiates Wake-up .................................................................................................................................. 25
3.6 CODEC RESET...............................................................................................................................................25
3.6.1 Cold AC ‘97 Reset ...............................................................................................................................25
3.6.2 Warm AC ‘97 Reset..............................................................................................................................25
3.6.3 Register AC ‘97 Reset..........................................................................................................................25
4. AC-link Digital Interface ..................................................................................................................................25
4.1 OVERVIEW....................................................................................................................................................25
4.2 AC-LINK SERIAL INTERFACE PROTOCOL......................................................................................................27
4.2.1 AC-link Variable Sample Rate Operation............................................................................................27
4.2.1.1 Variable Sample Rate Signaling Protocol ........................................................................................................ 27
4.2.1.2 SLOTREQ Behavior and Power Management................................................................................................. 28
4.2.2 Primary and Secondary Codec Register Addressing ...........................................................................28
4.3 AC-LINK OUTPUT FRAME (SDATA_OUT) ................................................................................................29
4.3.1 Slot 0: TAG / Codec ID.......................................................................................................................30
4.3.2 Slot 1: Command Address Port...........................................................................................................30
4.3.3 Slot 2: Command Data Port ...............................................................................................................31
4.3.4 Slot 3: PCM Playback Left Channel...................................................................................................31
4.3.5 Slot 4: PCM Playback Right Channel.................................................................................................31
4.3.6 Slot 5: Modem Line 1 Output Channel ...............................................................................................31
4.3.7 Slot 6: PCM Center DAC....................................................................................................................31
4.3.8 Slot 7: PCM L Surround DAC (or PCM L n+1).................................................................................32
AC ‘97 Component Specification Revision 2.3 Rev 1.0
4
4.3.9 Slot 8: PCM R Surround DAC (or PCM R n+1) ................................................................................32
4.3.10 Slot 9: PCM LFE DAC .......................................................................................................................32
4.3.11 Slot 10: Modem Line 2 Output Channel (or PCM L n+1, or S/PDIF output) ....................................32
4.3.12 Slot 11: Modem Handset Output Channel (or PCM R n+1, or S/PDIF output).................................32
4.3.13 Slot 12: Modem GPIO Control Channel (or PCM C n+1).................................................................32
4.3.14 Double Rate Audio in Slots 7, 8 or 10-12 ............................................................................................32
4.4 AC-LINK INPUT FRAME (SDATA_IN)........................................................................................................32
4.4.1 Slot 0: TAG ..........................................................................................................................................34
4.4.2 Slot 1: Status Address Port / SLOTREQ signaling bits.......................................................................34
4.4.2.1 Status Address Port .......................................................................................................................................... 34
4.4.2.2 SLOTREQ signaling bits ................................................................................................................................. 35
4.4.3 Slot 2: Status Data Port ......................................................................................................................35
4.4.4 Slot 3: PCM Record Left Channel ......................................................................................................35
4.4.5 Slot 4: PCM Record Right Channel....................................................................................................35
4.4.6 Slot 5: Modem Line 1 ADC..................................................................................................................36
4.4.7 Slot 6: Dedicated Microphone Record Data........................................................................................36
4.4.8 Slots 7-9: Vendor Reserved.................................................................................................................36
4.4.9 Slot 10: Modem Line 2 ADC................................................................................................................36
4.4.10 Slot 11: Modem Handset ADC.............................................................................................................36
4.4.11 Slot 12: Modem GPIO Status...............................................................................................................36
4.5 AC-LINK INTEROPERABILITY REQUIREMENTS AND RECOMMENDATIONS ....................................................36
4.5.1 “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data ...............................................................36
4.5.2 Codec Register Status Reads ...............................................................................................................37
4.5.3 Codec Register Status Read Completion Latency................................................................................37
4.5.4 The Codec-Ready Bit and Audio or Modem DAC/ADC Status Bits.....................................................38
5. Audio Features...................................................................................................................................................38
5.1 OVERVIEW....................................................................................................................................................38
5.2 LINE_OUT AND AUX_OUT.......................................................................................................................39
5.2.1 AUX_OUT Options..............................................................................................................................39
5.3 AUDIO SAMPLING RATE SUPPORT (FIXED, VARIABLE, AND DOUBLE) .........................................................39
5.4 MULTICHANNEL AUDIO................................................................................................................................40
5.4.1 Primary Codec Multichannel Audio ....................................................................................................40
5.4.2 Secondary Codec Multichannel Audio.................................................................................................40
5.4.2.1 Default Slot to DAC Mappings for Secondary Audio Codecs .........................................................................41
5.4.2.2 DAC Management across Multiple Audio Codecs .......................................................................................... 41
5.4.2.3 Volume Control across Multiple Audio Codecs............................................................................................... 42
5.4.2.4 Playback Synchronization across Multiple Audio Codecs ............................................................................... 42
5.5 AC ‘97 ANALOG MIXER ...............................................................................................................................42
5.5.1 Analog Mixer Output ...........................................................................................................................43
5.5.2 Analog Mixer Input..............................................................................................................................44
5.5.3 Analog Mixer Feature Detection .........................................................................................................44
5.5.3.1 Minimum Analog Mixer Feature Set ............................................................................................................... 44
5.5.3.2 Analog Mixer Cost-Reduction ......................................................................................................................... 44
5.5.3.3 Original Analog Mixer Options ....................................................................................................................... 44
5.6 SLOT ASSIGNMENTS FOR AUDIO...................................................................................................................45
5.7 BASELINE AUDIO REGISTER SET ..................................................................................................................46
5.7.1 Reset Register (Index 00h)...................................................................................................................48
5.7.2 Play Master Volume Registers (Index 02h, 04h and 06h)....................................................................49
5.7.3 Master Tone Control Registers (Index 08h) ........................................................................................50
5.7.4 PC Beep Register (Index 0Ah) .............................................................................................................51
5.7.5 Analog Mixer Input Gain Registers (Index 0Ch - 18h)........................................................................51
5.7.6 Record Select Control Register (Index 1Ah)........................................................................................52
5.7.7 Record Gain Registers (Index 1Ch and 1Eh).......................................................................................53
5.7.8 General Purpose Register (Index 20h) ................................................................................................53
5.7.9 3D Control Register (Index 22h) .........................................................................................................54
5.7.10 Audio Interrupt and Paging Mechanism (Index 24h) ..........................................................................54
5.7.11 Powerdown Control/Status Register (Index 26h) ................................................................................56
AC ‘97 Component Specification Revision 2.3 Rev 1.0
5
5.8 EXTENDED AUDIO REGISTER SET.................................................................................................................57
5.8.1 Extended Audio ID Register (Index 28h) .............................................................................................57
5.8.2 Extended Audio Status and Control Register (Index 2Ah) ...................................................................58
5.8.3 Audio Sample Rate Control Registers (Index 2Ch – 34h)....................................................................60
5.8.4 Surround and Center/LFE Volume Control Registers (Index 36h and 38h)........................................60
5.8.5 S/PDIF Control Register (Index 3Ah)..................................................................................................61
5.8.6 Vendor Reserved Registers (Index 5Ah - 5Fh, 70h - 7Ah)...................................................................62
5.8.7 Extended Codec Registers Page Structure Definition..........................................................................62
5.8.7.1 Extended Registers Page 00............................................................................................................................. 62
5.8.7.2 Extended Registers Page 01............................................................................................................................. 62
5.8.7.3 Extended Registers Page 02-0Fh...................................................................................................................... 62
5.8.8 Vendor ID Registers (Index 7Ch - 7Eh)...............................................................................................62
5.9 EXTENDED CODEC REGISTERS PAGE ‘01’ ....................................................................................................63
5.9.1 Discovery Descriptor Definition..........................................................................................................63
5.9.2 Audio Input/Output Capabilities Register............................................................................................64
5.9.2.1 Function Select Register (Index 66h)............................................................................................................... 65
5.9.2.2 Information and I/O Register (Index 68h)........................................................................................................ 65
5.9.2.3 Sense Register (Index 6Ah).............................................................................................................................. 67
5.9.3 Slot Mapping Descriptor .....................................................................................................................69
5.10 S/PDIF CONCURRENCY ................................................................................................................................70
5.10.1 Required concurrency support for S/PDIF transmission (48 kHz operation) .....................................71
5.10.1.1 Simultaneous DAC playback and S/PDIF transmission of a single 2-ch 48 kHz PCM stream.................... 71
5.10.1.2 Simultaneous DAC playback of a 2-ch 48 kHz PCM stream and S/PDIF transmission of an independent 48
kHz PCM or encoded multichannel stream ....................................................................................................................... 71
5.10.1.3 Secondary Codec supports simultaneous DAC playback of a 2-ch 48 kHz PCM stream and S/PDIF
transmission of an independent 48 kHz PCM or encoded multichannel stream ................................................................ 72
5.10.1.4 Primary or Secondary codec supports independent S/PDIF transmission of PCM or encoded stream on slots
10&11 ..................................................................................................................................................................... 72
5.10.2 Optional support for rates other than 48 kHz......................................................................................72
5.10.2.1 Simultaneous DAC playback and S/PDIF transmission of a single 2-ch non 48 kHz PCM stream............. 72
5.10.2.2 Simultaneous DAC playback and S/PDIF transmission of “bit exact” 32, 44.1, or 48 kHz PCM streams .. 72
6. Modem AFE Features .......................................................................................................................................73
6.1 OVERVIEW....................................................................................................................................................73
6.2 SLOT ASSIGNMENTS FOR MODEM ................................................................................................................73
6.3 GPIO PIN DEFINITIONS ................................................................................................................................74
6.3.1 GPIO Pin Implementation ...................................................................................................................74
6.3.2 Recommended Slot 12 GPIO Bit Definitions .......................................................................................75
6.4 MODEM CODEC COST REDUCTION OPTIONS ................................................................................................76
6.4.1 Elimination of the On-board Modem Speaker .....................................................................................76
6.4.2 Internal PHONE and MONO_OUT Connections (AMC ‘97 ) ............................................................76
6.5 WAKE-UP AND POWER MANAGEMENT EVENT (PME#) SUPPORT.................................................................77
6.5.1 Combined Audio/Modem AFE Codec (AMC ‘97 )...............................................................................77
6.5.2 Split Partitioned Implementations (AC ‘97 + MC ‘97 ) .....................................................................79
6.5.3 Wake-up and Voltage Sequencing .......................................................................................................79
6.5.4 Wake-up and Caller ID Decode in the Controller and/or Codec ........................................................79
6.6 MODEM AFE REGISTER DEFINITIONS ..........................................................................................................80
6.6.1 Extended Modem ID Register (Index 3Ch) ..........................................................................................80
6.6.2 Extended Modem Status and Control Register (Index 3Eh) ................................................................81
6.6.3 Modem Sample Rate Control Registers (Index 40h – 44h)..................................................................82
6.6.4 Modem DAC/ADC Level Control Registers (Index 46h – 4Ah)...........................................................83
6.6.5 GPIO Pin Configuration Register (Index 4Ch) ...................................................................................83
6.6.6 GPIO Pin Polarity/Type Register (Index 4Eh) ....................................................................................83
6.6.7 GPIO Pin Sticky Register (Index 50h) .................................................................................................83
6.6.8 GPIO Pin Wake-up Mask Register (Index 52h)...................................................................................84
6.6.9 GPIO Pin Status Register (Index 54h).................................................................................................84
6.6.10 Miscellaneous Modem AFE Status and Control Register (Index 56h) ................................................84
6.7 LOOPBACK MODES FOR TESTING ..................................................................................................................85
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