LPDDR4 JESD标准详解：低功耗内存技术规格

LPDDR4

5星 · 超过95%的资源需积分: 50 200 浏览量更新于2023-03-16 5 收藏 7.48MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源推荐

JEDEC Standard No. 209-4B

Page 12

2.2.9 254 ball e•MMC MCP Two-Channel FBGA (top view) using MO-276

NOTE 1 0.5 mm pitch, 24 rows.

NOTE 2 Top View, A1 in top left corner.

NOTE 3 ODT(ca)_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if

present) are disabled in the package.

NOTE 4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3 rank package, and for 1 rank and 2

rank package those balls are NC.

NOTE 5 The flash ball-out supports e•MMC 5.x.

NOTE 6 DRAM die pad VSS and VSSQ signals are combined to VSS package balls.

NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack.

NOTE 8 Vendor specific function (VSF) - this terminal should not have any external electrical connections, but it may

have an internal connection. The terminal may be routed to provide accessibility and may be used for general purpose

vendor specific operations.

12 3 4 5 6 7 8 9 101112 13 14 15 161718

DNU DNU DQ0_A VDD1 VDD2 VDDQ VDDQ VDD2 VDD1 VDDQ VDDQ VDD1 VDD1 DNU DNU A

DNU DQ1_A VSS VDDQ VSS DQ4_A VSS VDD2 VDD2 VDD2 VDD1 ZQ0 DNU B

C DQ2_A

VSS VSS DQ5_A VSS DQ7_A

DQS0_t

CA2_A

VSS CA5_A ZQ1 C

D DQ3_A

VSS DMI0_A VSS DQ6_A VSS

DQS0_c

CA3_A

VSS VSS ZQ2 D

E CA4_A

VSS CS0_A CKE0_A E

F CA1_A

VSS CS1_A CKE1_A F

G DQ13_A

VSS VSS VSS VDD2 VDD2 VDD2 VSS CA0_A VSS

CLK_c_

HDMI1_A

VSS VDDQ

DQ14_

VSS DQ15_A VDDQ VSS CS2_A VSS

CLK_t_

J DQ11_A

VDDQ VDDQ VSS DQ12_A VDDQ

DQS1_c

ODT(ca)_

CKE2_A

VCCQ VCCQ VCCQ J

VDD2 DQ10_A VSS DQ8_A DQ9_A VSS VSS

DQS1_t

VSSm VSSm VCCQ VSSm NC K

VDD2 VDD2 VDD2 VSSm DAT7 DAT6 VSSm VSSm VDDI L

VSF1 VSF3 VSF5 VSF7 VSF9 VSSm CMD DS VSSm VSSm DAT1 DAT4 VCC M

VSF2 VSF4 VSF6 VSF8 NC VSSm RST_n VSSm DAT2 DAT5 VSSm VSSm VCC N

VDD2 VDD2 VDD2 CLK VSSm VSSm DAT3 DAT0 VCC P

VDD2 DQ10_B VSS DQ8_B DQ9_B VSS VSS

DQS1_t

VCCQ VCCQ VSSm VSSm VSSm R

T DQ11_B

VDDQ VDDQ VSS DQ12_B VDDQ

DQS1_c

ODT(ca)_

CKE2_B

VCCQ VCCQ NC T

UDMI1_B

VSS VDDQ

DQ14_

VSS DQ15_B VDDQ VSS CS2_B VSS

CLK_t_

V DQ13_B

VSS VSS VSS VDD2 VDD2 VDD2 VSS CA0_B VSS

CLK_c_

W CA1_B

VSS CS1_B CKE1_B W

Y CA4_B

VSS CS0_B CKE0_B Y

AA DQ3_B

VSS DMI0_B VSS DQ6_B VSS

DQS0_c

CA3_B

VSS VSS

RESET_

AB DQ2_B

VSS VSS DQ5_B VSS DQ7_B

DQS0_t

CA2_B

VSS CA5_B NC AB

DNU DQ1_B VSS VDDQ VSS DQ4_B VSS VDD2 VDD2 VDD2 VDD1 NC DNU AC

DNU DNU DQ0_B VDD1 VDD2 VDDQ VDDQ VDD2 VDD1 VDDQ VDDQ VDD1 VDD1 DNU DNU AD

12 3 4 5 6 7 8 9 101112 13 14 15 161718

JEDEC Standard No. 209-4B

Page 13

2.2.10 254 ball UFS MCP Two-Channel FBGA (top view) using MO-276

NOTE 1 0.5 mm pitch, 24 rows.

NOTE 2 Top View, A1 in top left corner.

NOTE 3 ODT(ca)_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if

present) are disabled in the package.

NOTE 4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3 rank package, and for 1 rank and 2

rank package those balls are NC.

NOTE 5 DRAM die pad VSS and VSSQ signals are combined to VSS package balls.

NOTE 6 Package requires dual channel die or functional equivalent of single channel die-stack.

NOTE 7 Vendor specific function (VSF) - this terminal should not have any external electrical connections, but it may

have an internal connection. The terminal may be routed to provide accessibility and may be used for general purpose

vendor specific operations.

12 3 45 6 7 8 9101112131415161718

DNU DNU DQ0_A VDD1 VDD2 VDDQ VDDQ VDD2 VDD1 VDDQ VDDQ VDD1 VDD1 DNU DNU

B DNU DQ1_A VSS VDDQ VSS DQ4_A VSS VDD2 VDD2 VDD2 VDD1 ZQ0 DNU

CDQ2_AVSS VSS DQ5_A VSS DQ7_A DQS0_t_A CA2_A VSS CA5_A ZQ1

DDQ3_AVSS DMI0_A VSS DQ6_A VSS DQS0_c_A CA3_A VSS VSS ZQ2

E CA4_A VSS CS0_A CKE0_A

F CA1_A VSS CS1_A CKE1_A

GDQ13_AVSS VSS VSS VDD2 VDD2 VDD2 VSS CA0_A VSS CLK_c_A

H DMI1_A VSS VDDQ DQ14_A VSS DQ15_A VDDQ VSS CS2_A VSS CLK_t_A

JDQ11_AVDDQ VDDQ VSS DQ12_A VDDQ DQS1_c_A

ODT(ca)_

CKE2_A VCCQ2 VCCQ2 VCCQ2

K VDD2 DQ10_A VSS DQ8_A DQ9_A VSS VSS DQS1_t_A VSSm VSSm VCCQ2 VSSm

VDDIQ

L VDD2 VDD2 VDD2 VSSm DIN1_c DIN1_t VSSm VSSm VDDI

MNCVSF1 VSF3 VSF5 RFU VSSm RFU RST_n VSSm VSSm DIN0_c DIN0_t VCC

NNCVSF2 VSF4 VSF6 RFU VSSm RFU VSSm DOUT1_c DOUT1_t VSSm VSSm VCC

P VDD2 VDD2 VDD2 REF_CLK VSSm VSSm DOUT0_c DOUT0_t VCC

R VDD2 DQ10_B VSS DQ8_B DQ9_B VSS VSS DQS1_t_B VCCQ VCCQ VSSm VSSm VSSm

TDQ11_BVDDQ VDDQ VSS DQ12_B VDDQ DQS1_c_B

ODT(ca)_

CKE2_B VCCQ VCCQ VDDIQ

U DMI1_B VSS VDDQ DQ14_B VSS DQ15_B VDDQ VSS CS2_B VSS CLK_t_B

VDQ13_BVSS VSS VSS VDD2 VDD2 VDD2 VSS CA0_B VSS CLK_c_B

W CA1_B VSS CS1_B CKE1_B

Y CA4_B VSS CS0_B CKE0_B

AA DQ3_B VSS DMI0_B VSS DQ6_B VSS DQS0_c_B CA3_B VSS VSS RESET_n

AB DQ2_B

VSS VSS DQ5_B VSS DQ7_B DQS0_t_B CA2_B VSS CA5_B NC

DNU DQ1_B VSS VDDQ VSS DQ4_B VSS VDD2 VDD2 VDD2 VDD1 NC DNU

DNU DNU DQ0_B VDD1 VDD2 VDDQ VDDQ VDD2 VDD1 VDDQ VDDQ VDD1 VDD1 DNU DNU

12 3 45 6 7 8 9101112131415161718

JEDEC Standard No. 209-4B

Page 14

2.2.11 254 ball e•MMC MCP One Channel FBGA (top view) using MO-276

NOTE 1 0.5 mm pitch, 24 rows.

NOTE 2 Top View, A1 in top left corner.

NOTE 3 ODT(ca)_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if

present) are disabled in the package.

NOTE 4 ZQ2, CKE2_B, and CS2_B balls are reserved for 3 rank package, and for 1 rank and 2 rank package those

balls are NC.

NOTE 5 The flash ball-out supports e•MMC 5.x.

NOTE 6 DRAM die pad VSS and VSSQ signals are combined to VSS package balls.

NOTE 7 Vendor specific function (VSF) - this terminal should not have any external electrical connections, but it may

have an internal connection. The terminal may be routed to provide accessibility and may be used for general purpose

vendor specific operations.

12345678 9101112131415161718

DNU DNU NC NC NC NC NC NC NC NC NC NC NC DNU DNU A

DNU NC NC NC NC NC NC NC NC NC NC ZQ0 DNU B

C NC NC NC NC NC NC NC NC NC NC ZQ1 C

D NC NC NC NC NC NC NC NC NC NC ZQ2 D

E NC NC NC NC E

F NC NC NC NC F

G NC NC NC NC NC NC NC NC NC NC NC G

H NC NC NC NC NC NC NC NC NC NC NC H

J NC NC NC NC NC NC NC NC NC

VCCQ VCCQ VCCQ J

K NC NC NC NC NC NC NC NC

VSSm VSSm VCCQ VSSm NC K

L NC NC NC

VSSm DAT7 DAT6 VSSm VSSm VDDI L

VSF1 VSF3 VSF5 VSF7 VSF9 VSSm CMD DS VSSm VSSm DAT1 DAT4 VCC M

VSF2 VSF4 VSF6 VSF8 NC VSSm RST_n VSSm DAT2 DAT5 VSSm VSSm VCC N

VDD2 VDD2 VDD2 CLK VSSm VSSm DAT3 DAT0 VCC P

VDD2 DQ10_B VSS DQ8_B DQ9_B VSS VSS

DQS1_t

VCCQ VCCQ VSSm VSSm VSSm R

T DQ11_B

VDDQ VDDQ VSS

DQ12_

VDDQ

DQS1_c

ODT(ca)

CKE2_

VCCQ VCCQ NC T

U DMI1_B

VSS VDDQ

DQ14_

VSS DQ15_B VDDQ VSS CS2_B VSS

CLK_t

V DQ13_B

VSS VSS VSS VDD2 VDD2 VDD2 VSS CA0_B VSS

CLK_c

W CA1_B

VSS CS1_B

CKE1_

Y CA4_B

VSS CS0_B

CKE0_

AA DQ3_B

VSS

DMI0_

VSS DQ6_B VSS

DQS0_c

CA3_B

VSS VSS

RESET

AB DQ2_B

VSS VSS DQ5_B VSS DQ7_B

DQS0_t

CA2_B

VSS CA5_B NC AB

DNU DQ1_B VSS VDDQ VSS DQ4_B VSS VDD2 VDD2 VDD2 VDD1 NC DNU AC

DNU DNU DQ0_B VDD1 VDD2 VDDQ VDDQ VDD2 VDD1 VDDQ VDDQ VDD1 VDD1 DNU DNU AD

12345678 9101112131415161718

JEDEC Standard No. 209-4B

Page 16

2.4 ZQ Wiring

Standard LPDDR4 package ballmaps allocate one ZQ ball per die. Byte-Mode packages potentially

support more die for higher package memory density. In order to use ballmaps developed for Standard

LPDDR4, an alternate ZQ ball wiring strategy is employed when packages contain Byte-Mode devices as

shown in Figure 1.

Since this wiring strategy for Byte-Mode and Mixed packages shares a single ZQ resistor between ranks

and channels, applications must ensure that the ZQCal's do not overlap between the dies sharing the

resistor.

• Applications shall ensure that ZQCal_Start commands to one rank on any dies sharing a ZQ resistor

must complete (tZQCal satisfied) prior to issuing a ZQCal_Start command to a different rank tied to the

resistor. (Applications can satisfy this requirement, for example, by either:

- Issuing ZQCal_Start commands simultaneously to both DRAM channels

- Issuing ZQCal_Start commands to one DRAM channel only)

• DRAM shall ensure that ZQCal_Start can be sent independently to the two channels on a die. If a

ZQCal_Start command is received while a ZQ calibration is in progress on the die, the second

ZQCal_Start command will be ignored and the in progress calibration will not be interrupted.

(See 4.31.3, ZQ External Resistor, Tolerance, and Capacitive Loading, for more information.)

Figure 2 — ZQ Wiring Overview

2.4.1 Specific wiring notes for dual channel (x32) LPDDR4 packages

1. For packages using only standard devices

- ZQ0 is connected to rank 0 DRAM

- ZQ1 is connected to rank 1 DRAM (if present)

- ZQ2 is connected to rank 2 DRAM (if present)

2. For packages using only byte-mode devices

- ZQ0 is connected to all lower byte [7:0] or upper byte [15:8] DRAM(s)

- ZQ1 is connected to opposite byte of all DRAM(s) from ZQ0

- ZQ2 is NC

3. For packages using both standard and byte-mode devices

- ZQ0 is connected to all lower byte [7:0] or upper byte [15:8] DRAM(s)

- ZQ1 is connected to opposite byte of all DRAM(s) from ZQ0

- Standard DRAM(s) may be connected to either ZQ0 or ZQ1

- ZQ2 is NC

Multi-rank packages containing Byte Mode devices place additional loading on the I/O and power

topologies and therefore may not be appropriate for all application environments.

Standard Package Byte Mode Package Mixed Package

Rank2

Rank1

Rank0

DQ[15:0] DQ[7:0] DQ[15:8] DQ[7:0] DQ[15:8]

ZQ2

ZQ0

ZQ1

ZQ0

ZQ1

ZQ2- NCZQ2 - NC

ZQ0

Example

剩余306页未读，继续阅读

qianrunfa

粉丝: 4
资源: 6

会员权益专享

LPDDR4 JESD标准详解：低功耗内存技术规格

LPDDR4_JESD209-4

DDR4 PCB设计规范&设计要点

micron_lpddr4.pdf

K4UBE3D4AB-MGCL

jesd209-4b_lpddr4

jesd209-4b_low power double data rate 4 (lpddr4) .pdf

jesd209-5_4_3 lpddr5 lpddr4 lpddr3精解

lpddr4x spec手册

csdn lpddr5 spec

lpddr4x芯片接口协议jesd209-5

lpddr5 spec下载

lpddr4中文手册

lpddr5x( jesd209-5b)中文版.pdf

ddr4,lpddr4,lpddr4x

lpddr4x和lpddr4的区别

lpddr4和lpddr4x的区别

jesd2095 lpddr5.rar

lpddr4协议 csdn

lpddr4初始化流程

lpddr4pcb走线图

会员权益专享

最新资源