DDR_PHY_Interface_Specification_v3_0.pdf_内存子系统

接口

需积分: 25 108 浏览量更新于2023-03-16 评论 4 收藏 940KB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

DDR PHY Interface, Version 3.0 1 of 133

Cadence Design Systems, Inc.

DFI

DDR PHY Interface

DFI 3.0 Specification

18 May 2012

2 of 133 DDR PHY Interface, Version 3.0

Cadence Design Systems, Inc.

Release Information

Rev # Date Change

1.0 30 Jan 2007 Initial Release

2.0 17 Jul 2007 Modifications/Additions for DDR3 Support

2.0 21 Nov 2007 Additional modifications/additions for DDR3 support. Added read and

write leveling. Changes approved by the Technical Committee for DDR3

support.

2.0 21 Dec 2007 Removed references to data eye training for PHY Evaluation mode, added

a gate training-specific mode signal, corrected references and clarified

read

training.

2.0 11 Jan 2008 Modified wording; standardized notations in figures, clarified

terminology for read and write leveling.

2.0 26 Mar 2008 Added timing parameter t

rdlvl_en

and t

wrlvl_en

, signal dfi_rdlvl_edge

2.1 2 Oct 2008 Added initial LPDDR2 support and corrected minor errors from 2.0

release

2.1 24 Nov 2008 Added frequency change protocol, signal timing definitions, t

rdlvl_load

and

wrlvl_load

timing parameters and adjusted diagrams accordingly

2.1 30 Jan 2009 Added DFI logo

2.1 31 Mar 2009 Updated width of dfi_rdlvl_edge, corrected erroneous figures, updated

rdlvl_en

and t

wrlvl_en

definitions

2.1 20 May 2009 Added low power control interface, modified leveling request signal

description to include frequency change, added dfi_data_byte_disable

signal and t

phy_wrdata

timing parameters. Added DIMM support to the

status interface and updated frequency ratios from an example to a defined

method. Updated frequency ratios information for new proposals,

modified default values and requirements for some training interface

signals, incorporated LPDDR2 training operations changes

2.1 22 Jun 2009 Expanded frequency ratio information to include vectored read data,

expanded use of dfi_init_start, added timing diagrams for 1:4 frequency

ratio systems

2.1.1 23 Mar 2010 Added reference to the parity interface to the Overview. Changed

dfi_parity_in signal to have a phase index. Modified description of

dfi_freq_ratio signal to make it optional except for MCs/PHYs that

support multiple frequency ratios. Expanded figure 32 into two figures to

represent odd and even timing parameters.

2.1.1 01 Apr 2010 Changed minimum value for t

lp_wakeup

2.1.1 20 Apr 2010 Corrected figure 3 timing violation. Corrected erroneous sentence for 2T

timing. Corrected figure 35 t

phy_wrlat

timing. Correct incorrect references

to t

phy_wrlat

in frequency ratio read examples.

DDR PHY Interface, Version 3.0 3 of 133

Cadence Design Systems, Inc.

2.1.1 27 May 2010 Added Figure 4 and text to explain differences between Figure 3 and 4.

2.1.1 09 Jun 2010 Modified text in dfi_init_start and surrounding figures 3 and 4 for more

clarity.

3.0 21 May 2012 Added DDR4 DRAM support for: CRC, CA parity timing, CRC and CA

parity errors, DBI, leveling support, and CA modifications. Added DFI

read data rotation clarification, read data pointer resynchronization,

independent timing of DFI read data valid per data slice, data path chip

select, error interface, and programmable parameters. Renamed PHY

evaluation mode. Removed MC evaluation mode and t

phy_wrdelay

timing

parameter. Added support for refresh during training, multiple CS

training, enhancements to the update interface and the idle bus definition.

Proprietary Notice

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of Cadence.

Cadence makes no warranties with respect to this documentation and disclaims any implied

warranties of merchantability or fitness for a particular purpose. Information in this document is

subject to change without notice. Cadence assumes no responsibility for any errors that may appear

in this document.

Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly

disclaims, any representations or warranties as to the completeness, accuracy, or usefulness of the

information contained in this document. Cadence does not warrant that use of such information will

not infringe any third party rights, nor does Cadence assume any liability for damages or costs of

any kind that may result from use of such information.

RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in

subparagraphs (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS

252.227-7013.

Destination Control Statement

All technical data contained in this product is subject to the export control laws of the United States

of America. Disclosure to nationals of other countries contrary to United States law is prohibited.

It is the reader's responsibility to determine the applicable regulations and to comply with them.

Trademarks

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.

All other products or brand names mentioned are trademarks or registered trademarks of their

respective holders.

End User License Agreement2

1.Subject to the provisions of Clauses 2, 3, 4, 5 and 6, Cadence hereby grants to licensee

("Licensee") a perpetual, nonexclusive, nontransferable, royalty free, worldwide copyright license

to use and copy the DFI (DDR PHY Interface) specification (the "DFI Specification") for the

purpose of developing, having developed, manufacturing, having manufactured, offering to sell,

selling, supplying or otherwise distributing products which comply with the DFI Specification.

4 of 133 DDR PHY Interface, Version 3.0

Cadence Design Systems, Inc.

2.THE DFI SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES EXPRESS,

IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF

SATISFACTORY QUALITY, MERCHANTABILITY, NONINFRINGEMENT OR FITNESS

FOR A PARTICULAR PURPOSE.

3.No license, express, implied or otherwise, is granted to Licensee, under the provisions of Clause

1, to use Cadence's or any other person or entity participating in the development of the DFI

Specification listed herein (individually "Participant," collectively "Participants") trade name, or

trademarks in connection with the DFI Specification or any products based thereon. Nothing in

Clause 1 shall be construed as authority for Licensee to make any representations on behalf of

Cadence or the other Participants in respect of the DFI Specification.

4.NOTWITHSTANDING ANYTHING ELSE WILL CADENCE'S TOTAL AGGREGATE

LIABILITY FOR ANY CLAIM, SUIT, PROCEEDING OR OTHERWISE, RELATING IN

ANYWAY TO THE DFI SPECIFICATION EXCEED $1.00USD.

5.NOTWITHSTANDING ANYTHING ELSE WILL ANY PARTICIPANT'S TOTAL

AGGREGATE LIABILITY FOR ANY CLAIM, SUIT, PROCEEDING OR OTHERWISE,

RELATING IN ANYWAY TO THE DFI SPECIFICATION EXCEED $1.00USD.

6.Licensee agrees that Cadence and the Participants may use, copy, modify, reproduce and dist-

ribute any written comments or suggestions ("Communications") provided regarding the DFI

Specification by Licensee and that Licensee will not claim any proprietary rights in the DFI

Specification, or implementations thereof by any Participant or third party, as a result of the use of

the Communications in developing or changing the DFI Specification. Cadence and the

participants will have no confidentiality obligations with respect to the Communications and

Licensee will not include any confidential information of Licensee or any third party in any

Communications.

Participants

ARM Cadence Intel LSI Samsung ST Synopsys

DDR PHY Interface, Version 3.0 5 of 133

Cadence Design Systems, Inc.

CONTENTS

1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.0 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.0 Interface Signal Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.1 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.2 Write Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.1 Write Data Mask/Write DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.2 Write Data Chip Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.3 Write Data CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.4 Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.3 Read Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3.1 Read DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3.2 Read Data Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3.3 Read Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.4 Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.4 Update Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.5 Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

3.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

3.5.2 Clock Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.5.3 Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.5.4 Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.5.5 CRC and CA Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.6 DFI Training Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

3.6.1 Read Training Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

3.6.2 Write Leveling Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

3.6.3 dfi_lvl_pattern Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.6.4 Periodic Training Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

3.7 Low Power Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

3.8 Error Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.0 Functional Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.1 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.2 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.3 Data Bus Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4.4 Write Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.4.1 Write Transaction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.4.2 DBI - Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.4.3 Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.4.3.1 MC CRC Support (phycrc_mode ==0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.4.3.2 PHY CRC Support (phycrc_mode ==1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.4.3.3 Burst Chop 4 with PHY CRC Support (phycrc_mode ==1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.5 Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79