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ARMv8 Instruction Set Overview
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved. Page 1 of 112
ARMv8 Instruction Set Overview
Architecture Group
Document number:
PRD03-GENC-010197 15.0
Date of Issue: 11 November 2011
© Copyright ARM Limited 2009-2011. All rights reserved.
Abstract
This document provides a high-level overview of the ARMv8 instructions sets, being mainly the new A64
instruction set used in AArch64 state but also those new instructions added to the A32 and T32 instruction sets
since ARMv7-A for use in AArch32 state. For A64 this document specifies the preferred architectural assembly
language notation to represent the new instruction set.
Keywords
AArch64, A64, AArch32, A32, T32, ARMv8

ARMv8 Instruction Set Overview
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved. Page 2 of 112
Proprietary Notice
This specification is protected by copyright and the practice or implementation of the information herein may be
protected by one or more patents or pending applications. No part of this specification may be reproduced in any
form by any means without the express prior written permission of ARM. No license, express or implied, by
estoppel or otherwise to any intellectual property rights is granted by this specification.
Your access to the information in this specification is conditional upon your acceptance that you will not use or
permit others to use the information for the purposes of determining whether implementations of the ARM
architecture infringe any third party patents.
This specification is provided “as is”. ARM makes no representations or warranties, either express or implied,
included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that
the content of this specification is suitable for any particular purpose or that any practice or implementation of the
contents of the specification will not infringe any third party patents, copyrights, trade secrets, or other rights.
This specification may include technical inaccuracies or typographical errors.
To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation
any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages,
however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing,
modifying or any use of this specification, even if ARM has been advised of the possibility of such damages.
Words and logos marked with ® or TM are registered trademarks or trademarks of ARM Limited, except as
otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Copyright © 2009-2011 ARM Limited
110 Fulbourn Road, Cambridge, England CB1 9NJ
Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the
restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19.
This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the
acceptance by the recipient of, the conditions set out above.
In this document, where the term ARM is used to refer to the company it means “ARM or any of its subsidiaries as
appropriate”.

ARMv8 Instruction Set Overview
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved. Page 3 of 112
Contents
1 ABOUT THIS DOCUMENT 6
1.1 Change control 6
1.1.1 Current status and anticipated changes 6
1.1.2 Change history 6
1.2 References 6
1.3 Terms and abbreviations 7
2 INTRODUCTION 8
3 A64 OVERVIEW 8
3.1 Distinguishing 32-bit and 64-bit Instructions 10
3.2 Conditional Instructions 10
3.3 Addressing Features 11
3.3.1 Register Indexed Addressing 11
3.3.2 PC-relative Addressing 11
3.4 The Program Counter (PC) 11
3.5 Memory Load-Store 11
3.5.1 Bulk Transfers 11
3.5.2 Exclusive Accesses 12
3.5.3 Load-Acquire, Store-Release 12
3.6 Integer Multiply/Divide 12
3.7 Floating Point 12
3.8 Advanced SIMD 13
4 A64 ASSEMBLY LANGUAGE 14
4.1 Basic Structure 14
4.2 Instruction Mnemonics 14
4.3 Condition Codes 15
4.4 Register Names 17
4.4.1 General purpose (integer) registers 17
4.4.2 FP/SIMD registers 18
4.5 Load/Store Addressing Modes 20
5 A64 INSTRUCTION SET 21

ARMv8 Instruction Set Overview
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved. Page 4 of 112
5.1 Control Flow 22
5.1.1 Conditional Branch 22
5.1.2 Unconditional Branch (immediate) 22
5.1.3 Unconditional Branch (register) 22
5.2 Memory Access 23
5.2.1 Load-Store Single Register 23
5.2.2 Load-Store Single Register (unscaled offset) 24
5.2.3 Load Single Register (pc-relative, literal load) 25
5.2.4 Load-Store Pair 25
5.2.5 Load-Store Non-temporal Pair 26
5.2.6 Load-Store Unprivileged 27
5.2.7 Load-Store Exclusive 28
5.2.8 Load-Acquire / Store-Release 29
5.2.9 Prefetch Memory 31
5.3 Data Processing (immediate) 32
5.3.1 Arithmetic (immediate) 32
5.3.2 Logical (immediate) 33
5.3.3 Move (wide immediate) 34
5.3.4 Address Generation 35
5.3.5 Bitfield Operations 35
5.3.6 Extract (immediate) 37
5.3.7 Shift (immediate) 37
5.3.8 Sign/Zero Extend 37
5.4 Data Processing (register) 37
5.4.1 Arithmetic (shifted register) 38
5.4.2 Arithmetic (extending register) 39
5.4.3 Logical (shifted register) 40
5.4.4 Variable Shift 42
5.4.5 Bit Operations 43
5.4.6 Conditional Data Processing 43
5.4.7 Conditional Comparison 45
5.5 Integer Multiply / Divide 46
5.5.1 Multiply 46
5.5.2 Divide 47
5.6 Scalar Floating-point 48
5.6.1 Floating-point/SIMD Scalar Memory Access 48
5.6.2 Floating-point Move (register) 51
5.6.3 Floating-point Move (immediate) 51
5.6.4 Floating-point Convert 51
5.6.5 Floating-point Round to Integral 56
5.6.6 Floating-point Arithmetic (1 source) 57
5.6.7 Floating-point Arithmetic (2 source) 57
5.6.8 Floating-point Min/Max 58
5.6.9 Floating-point Multiply-Add 58
5.6.10 Floating-point Comparison 59
5.6.11 Floating-point Conditional Select 59
5.7 Advanced SIMD 60
5.7.1 Overview 60
5.7.2 Advanced SIMD Mnemonics 61
5.7.3 Data Movement 61

ARMv8 Instruction Set Overview
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved. Page 5 of 112
5.7.4 Vector Arithmetic 62
5.7.5 Scalar Arithmetic 67
5.7.6 Vector Widening/Narrowing Arithmetic 70
5.7.7 Scalar Widening/Narrowing Arithmetic 73
5.7.8 Vector Unary Arithmetic 73
5.7.9 Scalar Unary Arithmetic 75
5.7.10 Vector-by-element Arithmetic 76
5.7.11 Scalar-by-element Arithmetic 78
5.7.12 Vector Permute 78
5.7.13 Vector Immediate 79
5.7.14 Vector Shift (immediate) 80
5.7.15 Scalar Shift (immediate) 82
5.7.16 Vector Floating Point / Integer Convert 84
5.7.17 Scalar Floating Point / Integer Convert 84
5.7.18 Vector Reduce (across lanes) 85
5.7.19 Vector Pairwise Arithmetic 86
5.7.20 Scalar Reduce (pairwise) 86
5.7.21 Vector Table Lookup 87
5.7.22 Vector Load-Store Structure 88
5.7.23 AArch32 Equivalent Advanced SIMD Mnemonics 91
5.7.24 Crypto Extension 99
5.8 System Instructions 100
5.8.1 Exception Generation and Return 100
5.8.2 System Register Access 101
5.8.3 System Management 101
5.8.4 Architectural Hints 104
5.8.5 Barriers and CLREX 104
6 A32 & T32 INSTRUCTION SETS 106
6.1 Partial Deprecation of IT 106
6.2 Load-Acquire / Store-Release 106
6.2.1 Non-Exclusive 106
6.2.2 Exclusive 107
6.3 VFP Scalar Floating-point 108
6.3.1 Floating-point Conditional Select 108
6.3.2 Floating-point minNum/maxNum 108
6.3.3 Floating-point Convert (floating-point to integer) 108
6.3.4 Floating-point Convert (half-precision to/from double-precision) 109
6.3.5 Floating-point Round to Integral 109
6.4 Advanced SIMD Floating-Point 110
6.4.1 Floating-point minNum/maxNum 110
6.4.2 Floating-point Convert 110
6.4.3 Floating-point Round to Integral 110
6.5 Crypto Extension 111
6.6 System Instructions 112
6.6.1 Halting Debug 112
6.6.2 Barriers and Hints 112
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