ARMv8指令集详解：A64与AArch32状态的新特性

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"ARMv8_ISA_Overview（ARMv8指令集概述）.pdf - 提供了ARMv8指令集的高级概览，主要聚焦于64位的A64指令集，同时也涵盖了在AArch32状态下使用的A32和T32指令集的新指令。文档描述了A64的架构级汇编语言表示法，并提到了关键词AArch64、A64、AArch32、A32、T32以及ARMv8。" ARMv8指令集是ARM架构的重要组成部分，它是从ARMv7-A演进而来，引入了一种新的64位指令集——A64，用于64位的AArch64状态。A64指令集的设计目标是为了提高性能和效率，特别是针对服务器、数据中心和高性能计算等应用。在AArch64状态下，程序可以利用更多的地址空间和更高效的指令编码来实现性能提升。除了A64，该文档也涵盖了在32位AArch32状态下使用的A32和T32指令集的更新。A32是传统的THUMB-2指令集的扩展，而T32是一种更高效的16位变体，用于减少代码大小。在ARMv8中，这些指令集得到了增强，添加了一些新的指令，以支持新特性并提高32位代码的性能。 ARMv8架构还引入了对向量处理的支持，如AdvancedSIMD（也称为NEON），它在多媒体处理、图像处理和科学计算等领域中扮演关键角色。此外，还包括浮点运算的改进，提供更强大的单指令多数据（SIMD）操作。文档中描述的“首选架构级汇编语言表示法”是指用于编写和理解A64指令的汇编语法。汇编语言是低级编程的一种形式，允许程序员直接控制硬件操作，对于理解和调试底层系统代码非常有用。 ARMv8指令集的一个关键特性是其二进制兼容性，允许软件在32位和64位模式之间无缝切换，这被称为“二进制兼容性层”。这种设计确保了从ARMv7到ARMv8的平滑过渡，使得开发者能够为新的64位平台优化代码，同时保持对旧软件的兼容性。总结来说，"ARMv8_ISA_Overview"提供了关于ARMv8指令集的全面介绍，包括64位的A64指令集和32位的A32与T32指令集的更新。这个文档是理解ARMv8架构和开发相关软件的关键资源，特别适合那些需要深入理解每条指令功能的工程师和开发者。

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ARMv8 Instruction Set Overview

PRD03-GENC-010197

2. Instructions which are truly conditionally executed (i.e. when the condition is false they have no effect on

the architectural state, aside from advancing the program counter) have the condition appended to the

instruction with a '.' delimiter. For example B.EQ.

3. If there is more than one instruction extension, then the conditional extension is always last.

4. Where a conditional instruction has qualifiers, the qualifiers follow the condition.

5. Instructions which are unconditionally executed, but use the condition flags as a source operand, will

specify the condition to test in their final operand position, e.g. CSEL Wd,Wm,Wn,NE

To aid portability an A64 assembler may also provide the old UAL conditional mnemonics, so long as they have

direct equivalents in the A64 ISA. However, the UAL mnemonics will not be generated by an A64 disassembler –

their use is deprecated in 64-bit assembler code, and may cause a warning or error if backward compatibility is

not explicitly requested by the programmer.

The full list of condition codes is as follows:

Encoding

Name

alias)

Meaning (integer) Meaning (floating point) Flags

0000 EQ

Equal Equal

Z==1

0001 NE

Not equal Not equal, or unordered

Z==0

0010

(CS)

Unsigned higher or same

(Carry set)

Greater than, equal, or unordered

C==1

0011

(CC)

Unsigned lower

(Carry clear)

Less than

C==0

0100 MI

Minus (negative) Less than

N==1

0101 PL

Plus (positive or zero) Greater than, equal, or unordered

N==0

0110 VS

Overflow set Unordered

V==1

0111 VC

Overflow clear Ordered

V==0

1000 HI

Unsigned higher Greater than, or unordered

C==1 && Z==0

1001 LS

Unsigned lower or same Less than or equal

!(C==1 && Z==0)

1010 GE

Signed greater than or

equal

Greater than or equal

N==V

1011 LT

Signed less than Less than or unordered

N!=V

1100 GT

Signed greater than Greater than

Z==0 && N==V

1101 LE

Signed less than or equal Less than, equal, or unordered

!(Z==0 && N==V)

1110 AL

1111 NV

†

Always Always

Any

†The condition code NV exists only to provide a valid disassembly of the ‘1111b’ encoding, and otherwise behaves

identically to AL.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.4 Register Names

4.4.1 General purpose (integer) registers

The thirty one general purpose registers in the main integer register bank are named R0 to R30, with special

registers are used in a specific instruction form, they must be further qualified to indicate the operand data size (32

or 64 bits) – and hence the instruction’s data size.

The qualified names for the general purpose registers are as follows, where ‘n’ is the register number 0 to 30:

Size (bits)

32b 64b

Name

Wn Xn

Where register number 31 represents read zero or discard result (aka the “zero register”):

Size (bits)

32b 64b

Name

WZR XZR

Where register number 31 represents the stack pointer:

Size (bits)

32b 64b

Name

WSP

In more detail:

• The names Xn and Wn refer to the same architectural register.

• There is no register named W31 or X31.

• For instruction operands where register 31 in interpreted as the 64-bit stack pointer, it is represented by

the name SP. For operands which do not interpret register 31 as the 64-bit stack pointer this name shall

cause an assembler error.

• The name WSP represents register 31 as the stack pointer in a 32-bit context. It is provided only to allow a

valid disassembly, and should not be seen in correctly behaving 64-bit code.

• For instruction operands which interpret register 31 as the zero register, it is represented by the name XZR

in 64-bit contexts, and WZR in 32-bit contexts. In operand positions which do not interpret register 31 as

the zero register these names shall cause an assembler error.

• Where a mnemonic is overloaded (i.e. can generate different instruction encodings depending on the data

size), then an assembler shall determine the precise form of the instruction from the size of the first

some cases a register may have a different size (e.g. an address base register is always 64 bits), and a

source register may be smaller than the destination if it contains a word, halfword or byte that is being

widened by the instruction to 64 bits.

• The architecture does not define a special name for register 30 that reflects its special role as the link

Standard.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.4.2 FP/SIMD registers

The thirty two registers in the FP/SIMD register bank named V0 to V31 are used to hold floating point

operands for the scalar floating point instructions, and both scalar and vector operands for the Advanced

SIMD instructions. As with the general purpose integer registers, when they are used in a specific instruction

form the names must be further qualified to indicate the data shape (i.e. the data element size and number of

elements or lanes) held within them.

Note however that the data type, i.e. the interpretation of the bits within each register or vector element –

integer (signed, unsigned or irrelevant), floating point, polynomial or cryptographic hash – is not described by

the register name, but by the instruction mnemonics which operate on them. For more details see the

Advanced SIMD description in §5.7.

4.4.2.1 SIMD scalar register

In Advanced SIMD and floating point instructions which operate on scalar data the FP/SIMD registers behave

similarly to the main general-purpose integer registers, i.e. only the lower bits are accessed, with the unused

high bits ignored on a read and set to zero on a write. The qualified names for scalar FP/SIMD names indicate

the number of significant bits as follows, where ‘n’ is a register number 0 to 31:

Size (bits)

8b 16b

32b 64b 128b

Name

Bn Hn Sn Dn Qn

4.4.2.2 SIMD vector register

When a register holds multiple data elements on which arithmetic will be performed in a parallel, SIMD

fashion, then a qualifier describes the vector shape: i.e. the element size, and the number of elements or

“lanes”. Where “bits



lanes” does not equal 128, the upper 64 bits of the register are ignored when read and

set to zero on a write.

The fully qualified SIMD vector register names are as follows, where ‘n’ is the register number 0 to 31:

Shape (bits



lanes)



8 8b



16 16b



16b



32b



32b



4 64b



1 64b



Name

Vn.8B Vn.16B Vn.4H Vn.8H Vn.2S Vn.4S Vn.1D Vn.2D

4.4.2.3 SIMD vector element

Where a single element from a SIMD vector register is used as a scalar operand, this is indicated by

appending a constant, zero-based “element index” to the vector register name, inside square brackets. The

number of lanes is not represented, since it is not encoded, and may only be inferred from the index value.

Size (bits)

8b 16b 32b 64b

Name

Vn.B[i] Vn.H[i] Vn.S[i] Vn.D[i]

However an assembler shall accept a fully qualified SIMD vector register name as in §4.4.2.2, so long as the

number of lanes is greater than the index value. For example the following forms will both be accepted by an

assembler as the name for the 32-bit element in bits <63:32> of SIMD register 9:

V9.S[1] standard disassembly

V9.2S[1] optional number of lanes

V9.4S[1] optional number of lanes

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.5 Load/Store Addressing Modes

Load/store addressing modes in the A64 instruction set broadly follows T32 consisting of a 64-bit base register

(Xn or SP) plus an immediate or register offset.

Type Immediate Offset

Simple register (exclusive)

[base{,#0}]

n/a n/a

Offset

[base{,#imm}] [base,Xm{,LSL #imm}] [base,Wm,(S|U)XTW {#imm}]

Pre-indexed

[base,#imm]!

n/a n/a

Post-indexed

[base],#imm

n/a n/a

PC-relative (literal) load

label

n/a n/a

• An immediate offset is encoded in various ways, depending on the type of load/store instruction:

Bits Sign Scaling Write-

back?

Load/Store Type

0 -

- - exclusive / acquire / release

7 signed

scaled option register pair

9 signed

unscaled option single register

12 unsigned

scaled no single register

• Where an immediate offset is scaled, it is encoded as a multiple of the data access size (except PC-

relative loads, where it is always a word multiple). The assembler always accepts a byte offset, which is

converted to the scaled offset for encoding, and a disassembler decodes the scaled offset encoding and

displays it as a byte offset. The range of byte offsets supported therefore varies according to the type of

load/store instruction and the data access size.

• The "post-indexed" forms mean that the memory address is the base register value, then base plus

offset is written back to the base register.

• The "pre-indexed" forms mean that the memory address is the base register value plus offset, then the

computed address is written back to the base register.

• A “register offset” means that the memory address is the base register value plus the value of 64-bit index

• An “extended register offset” means that the memory address is the base register value plus the value of

32-bit index register Wm, sign or zero extended to 64 bits, then optionally scaled by the access size.

• An assembler should accept Xm as an extended index register, though Wm is preferred.

• The pre/post-indexed forms are not available with a register offset.

• There is no "down" option, so subtraction from the base register requires a negative signed immediate

offset (two's complement) or a negative value in the index register.

• When the base register is SP the stack pointer is required to be quadword (16 byte, 128 bit) aligned prior

to the address calculation and write-backs – misalignment will cause a stack alignment fault. The stack

pointer may not be used as an index register.

• Use of the program counter (PC) as a base register is implicit in literal load instructions and not permitted

in other load or store instructions. Literal loads do not include byte and halfword forms. See section 5

below for the definition of label.

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