DRV8313
SLVSBA5A –OCTOBER 2012–REVISED NOVEMBER 2012
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PIN DESCRIPTIONS (continued)
PIN
TYPE DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
Output
OUT1 5 O Output 1
OUT2 8 O Output 2 Connect to loads.
OUT3 9 O Output 3
PGND1 6 – Ground for OUT1
PGND2 7 – Ground for OUT2 Connect to ground, or to low-side current-sense resistors.
PGND3 10 – Ground for OUT3
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)
VALUE UNIT
Power-supply voltage range (V
M
) –0.3 V to 65 V
Digital-pin voltage range –0.5 to 7 V
Comparator input-voltage range –0.5 to 7 V
Peak motor-drive output current Internally limited A
Pin voltage (GND1, GND2, GND3) ±600 mV
Continuous motor-drive output current
(3)
2.5 A
T
J
Operating virtual junction temperature range –40 to 150 ºC
T
stg
Storage temperature range –60 to 150 ºC
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
(3) Observe power dissipation and thermal limits.
THERMAL INFORMATION
DRV8313
THERMAL METRIC
(1)
PWP UNIT
28 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
31.6 °C/W
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
15.9 °C/W
θ
JB
Junction-to-board thermal resistance
(4)
5.6 °C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.2 °C/W
ψ
JB
Junction-to-board characterization parameter
(6)
5.5 °C/W
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
1.4 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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