MPC5746CRM.pdf

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NXP Semiconductors

Document Number: MPC5746CRM

Rev. 4.1, 02/2017

This is the MPC5746C Reference Manual set, consisting of the following files:

• MPC5746C RM Addendum, Rev. 1

• MPC5746C Reference Manual, Rev. 4

MPC5746C Reference Manual

Contents

Section number Title Page

Chapter 1

Addendum for Rev. 4 of MPC5746CRM

1.1 Introduction.....................................................................................................................................................................5

Chapter 2

RM Addendum Rev 1

2.1 System memory map.......................................................................................................................................................9

2.2 PAD keeping feature in LPU/STANDBY mode............................................................................................................ 10

2.3 FPREG voltage regulator................................................................................................................................................13

2.4 Voltage monitoring.........................................................................................................................................................15

2.5 Crossbar Switch configuration........................................................................................................................................17

2.6 Memory Map and Registers............................................................................................................................................18

2.6.1

Region Descriptor n, Word 2 Format 1 (SMPU_RD_nW2_F1)....................................................................... 20

2.6.2

Region Descriptor n, Word 2 Format 0 (SMPU_RD_nW2_F0)....................................................................... 22

2.6.3

Region Descriptor n, Word 3 (SMPU_RGDn_WRD3).....................................................................................24

2.7 Application information..................................................................................................................................................25

2.8 Memory Map and Registers............................................................................................................................................28

2.8.1 INTC Master Protection Register (INTC_MPROT)..........................................................................................28

2.9 Unified Channels Memory Map and Registers...............................................................................................................29

2.9.1

eMIOS UC Control register n (eMIOS_Cn)......................................................................................................30

2.10 Introduction.....................................................................................................................................................................36

2.11 LIN mode features.......................................................................................................................................................... 36

2.12 Memory Map and Registers............................................................................................................................................37

2.12.1

Password Group n - Lock 0 Status Register (PASS_LOCK0_PGn)................................................................. 38

2.12.2

Password Group n - Lock 1 Status Register (PASS_LOCK1_PGn)................................................................. 39

2.12.3

Password Group n - Lock 2 Status Register (PASS_LOCK2_PGn)................................................................. 41

2.12.4

Password Group n - Lock 3 Status Register (PASS_LOCK3_PGn)................................................................. 42

MPC5746C Reference Manual Addendum, Rev. 1, 02/2017

NXP Semiconductors 3