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aardvark-v4.00用户手册.pdf
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更新于2023-05-26
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Aardvark I2C/SPI主机适配器允许开发者通过自己定义一个Windows,Linux,或者Mac OS X Pc 到的嵌入式系统,支持Master-Slave 用I2C和 SPI规程传送串行规范标准。Aardvark I2C/SPI主机适配器可用于工业,汽车,消费,医疗电子等 各领域的I2C/SPI应用的开发和芯品烧录。
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Aardvark I
2
C/SPI Embedded Systems Interface
Features
• I
2
C – Two wire interface
• Standard mode (100 kbps) and fast mode (400 kbps)
• Variable bitrate (1-800 kbps)
• Byte throughput rates are near theoretical maximums
• Master transmit and receive
• Asynchronous slave transmit and receive
• Repeated start, 10-bit addressing, and combined format
• SPI – 4 wire serial communication protocol
• Up to 8 Mbps master signaling rate
• Up to 4 Mbps slave signaling rate
• Full duplex master transmit/receive
• Asynchronous slave transmit/receive
• Configurable slave select polarity for master mode
• GPIO – General Purpose Input/Output
• General purpose signaling on I2C and/or SPI pins
• Internal caching of GPIO configuration
• I
2
C Monitor
• Unobtrusively record traffic on an I2C bus
• Supports bus speeds up to 125 kHz
• USB host communication
• Up to 3 Mbps transfer to host PC
• Powered from USB, eliminating power adapters
• Reports as a full-speed device (12 Mbps) to USB 2.0 hosts
• Software API
• Linux and Windows compatible
• Easy to integrate application interface
• Upgradeable Firmware
• Field upgradeable over USB
• Error checking prevents upgrade disasters
Summary
The Aardvark I
2
C/SPI Embedded Systems Interface is a host adapter through
USB. It allows a developer to interface a host PC to a downstream embedded sys-
tem environment and transfer serial messages using the I
2
C and SPI protocols.
I
2
C and SPI functionality can be used concurrently. Additionally, the I
2
C and/or
SPI pins can be used for general purpose signaling when the respective subsys-
tem is not in use. An I
2
C monitoring feature is also available to unobtrusively
record traffic on an I
2
C bus.
I
2
C/SPI
AARDVARK
Aardvark I
2
C/SPI
Embedded Systems Interface
Data Sheet v4.00
April 20, 2007
www.totalphase.com © 2003–2007 Total Phase, Inc.

Aardvark I
2
C/SPI Embedded Systems Interface
1 General Overview
1.1 I
2
C Background
I
2
C History
When connecting multiple devices to a microcontroller, the address and data lines of each
devices were conventionally connected individually. This would take up precious pins on the
microcontroller, result in a lot of traces on the PCB, and require more components to connect
everything together. This made these systems expensive to produce and susceptible to inter-
ference and noise.
To solve this problem, Philips developed Inter-IC bus, or I
2
C , in the 1980s. I
2
C is a low-
bandwidth, short distance protocol for on board communications. All devices are connected
through two wires: serial data (SDA) and serial clock (SCL).
Master
Slave Slave Slave
SDA
SCL
Figure 1: Sample I
2
C Implementation.
Regardless of how many slave units are attached to the I
2
C bus, there are only two signals connected to
all of them. Consequently, there is additional overhead because an addressing mechanism is required
for the master device to communicate with a specific slave device.
Because all commnication takes place on only two wires, all devices must have a unique ad-
dress to identify it on the bus. Slave devices have a predefined address, but the lower bits of
the address can be assigned to allow for multiples of the same devices on the bus.
I
2
C Theory of Operation
I
2
C has a master/slave protocol. The master initiates the communication. Here is a simplified
description of the protocol. For precise details, please refer to the Philips I
2
C specification. The
sequence of events are as follows:
1. The master device issues a start condition. This condition informs all the slave devices
to listen on the serial data line for their respective address.
2. The master device sends the address of the target slave device and a read/write flag.
3. The slave device with the matching address responds with an acknowledgment signal.
4. Communication proceeds between the master and the slave on the data bus. Both the
master and slave can receive or transmit data depending on whether the communication
is a read or write. The transmitter sends 8 bits of data to the receiver, which replies with
a 1 bit acknowledgment.
www.totalphase.com 2

Aardvark I
2
C/SPI Embedded Systems Interface
5. When the communication is complete, the master issues a stop condition indicating that
everything is done.
Figure 2 shows a sample bitstream of the I
2
C protocol.
START
Slave Address
READ/
WRITE
ACK
STOPData Data
ACK
NAK/
ACK
Figure 2: I
2
C Protocol.
Since there are only two wires, this protocol includes the extra overhead of the addressing and acknowl-
edgement mechanisms.
I
2
C Features
I
2
C has many features other important features worth mentioning. It supports multiple data
speeds: standard (100 kbps), fast (400 kbps) and high speed (3.4 Mbps) communications.
Other features include:
• Built in collision detection,
• 10-bit Addressing,
• Multi-master support,
• Data broadcast (general call).
For more information about other features, see the references at the end of this section.
I
2
C Benefits and Drawbacks
Since only two wires are required, I
2
C is well suited for boards with many devices connected
on the bus. This helps reduce the cost and complexity of the circuit as additional devices are
added to the system.
Due to the presence of only two wires, there is additional complexity in handling the overhead
of addressing and acknowledgments. This can be inefficient in simple configurations and a
direct-link interface such as SPI might be preferred.
I
2
C References
• I
2
C bus – NXP (Philips) Semiconductors Official I
2
C website
• I
2
C (Inter-Integrated Circuit) Bus Technical Overview and Frequently Asked Questions –
Embedded Systems Academy
• Introduction to I
2
C – Embedded.com
• I
2
C – Open Directory Project Listing
www.totalphase.com 3

Aardvark I
2
C/SPI Embedded Systems Interface
1.2 SPI Background
SPI History
SPI is a serial communication bus developed by Motorola. It is a full-duplex protocol which
functions on a master-slave paradigm that is ideally suited to data streaming applications.
SPI Theory of Operation
SPI requires four signals: clock (SCLK), master output/slave input (MOSI), master input/slave
output (MISO), slave select (SS).
Slave 1
SCLK
MOSI
MISO
SS
Master
SCLK
MOSI
MISO
SS1
SS2
SS3
Slave 2
SCLK
MOSI
MISO
SS
Slave 3
SCLK
MOSI
MISO
SS
Figure 3: Sample SPI Implementation.
Each slave device requires a separate slave select signal (SS). This means that as devices are added,
the circuit increases in complexity.
Three signals are shared by all devices on the SPI bus: SCLK, MOSI and MISO. SCLK is
generated by the master device and is used for synchronization. MOSI and MISO are the data
lines. The direction of transfer is indicated by their names. Data is always transferred in both
directions in SPI, but an SPI device interested in only transmitting data can choose to ignore
the receive bytes. Likewise, a device only interested in the incoming bytes can transmit dummy
bytes.
Each device has its own SS line. The master pulls low on a slave’s SS line to select a device
for communication.
The exchange itself has no pre-defined protocol. This makes it ideal for data-streaming appli-
cations. Data can be transferred at high speed, often into the range of the tens of megahertz.
The flipside is that there is no acknowledgment, no flow control, and the master may not even
be aware of the slave’s presence.
www.totalphase.com 4

Aardvark I
2
C/SPI Embedded Systems Interface
SPI Modes
Although there is no protocol, the master and slave need to agree about the data frame for the
exchange. The data frame is described by two parameters: clock polarity (CPOL) and clock
phase (CPHA). Both parameters have two states which results in four possible combinations.
These combinations are shown in figure 4.
MODE 0
Clock Phase (CPHA)
Clock Polarity (CPOL)
CPHA = 0
CPOL = 0CPOL = 1
CPHA = 1
MODE 2
MODE 1
MODE 3
sample sample
sample sample
Figure 4: SPI Modes
The frame of the data exchange is descr ibed by two parameters, the clock polarity (CPOL) and the clock
phase (CPHA). This diagram shows the four possible states for these parameters and the corresponding
mode in SPI.
SPI Benefits and Drawbacks
SPI is a ver y simple communication protocol. It does not have a specific high-level protocol
which means that there is almost no overhead. Data can be shifted at very high rates in full
duplex. This makes it very simple and efficient in a single master single slave scenario.
Because each slave needs its own SS, the number of traces required is n+3, where n is the
number of SPI devices. This means increased board complexity when the number of slaves is
increased.
SPI References
• Introduction to Serial Peripheral Interface – Embedded.com
• SPI – Serial Peripheral Interface
www.totalphase.com 5
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