library ieee;
use ieee.std_logic_1164.all;
enty comp4 is
port( A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
M,G,L: out std_logic);
end comp4;
architecture behave of comp4 is
begin
p1: process(A,B)
begin
if(A=B)then M<='1';G<='0';L<='0';
elsif(A>B)then M<='0';G<='1';L<='0';
elsif(A<B)then M<='0';G<='0';L<='1';
end if;
end process p1;
end behave;
二、 仿真波形
三、 管脚分配
