msp430x16x.h

MSP430

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/******************************************************************************/

/* Legacy Header File */

/* Not recommended for use in new projects. */

/* Please use the msp430.h file or the device specific header file */

/******************************************************************************/

/********************************************************************

* Standard register and bit definitions for the Texas Instruments

* MSP430 microcontroller.

* This file supports assembler and C development for

* MSP430x16x devices.

* Texas Instruments, Version 2.7

* Rev. 2.0, Fixed definitions for DMA

* Rev. 2.1, Alignment of defintions in Users Guide and of version numbers

* Rev. 2.2, Fixed definitions for I2C

* Rev. 2.21,Fixed definitions for I2C for assembler

* Rev. 2.3, Fixed type in ADC12 bit definitions (replaced ADC10 with ADC12)

* Added SVS

* Added DMA request definitions

* Rev. 2.4, Removed unused def of TASSEL2 / TBSSEL2

* Rev. 2.5, Added VLD bits in SVS module

* Rev. 2.6, Fixed incorrect bits in I2C STT (wrong:SST) and I2C prefix was missing at some bits

* Rev. 2.7, added definitions for Interrupt Vectors xxIV

********************************************************************/

#ifndef __msp430x16x

#define __msp430x16x

#ifdef __IAR_SYSTEMS_ICC__

#ifndef _SYSTEM_BUILD

#pragma system_include

#endif

#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */

#error msp430x16x.h file for use with ICC430/A430 only

#endif

/************************************************************

* STATUS REGISTER BITS

************************************************************/

#define C (0x0001u)

#define Z (0x0002u)

#define N (0x0004u)

#define V (0x0100u)

#define GIE (0x0008u)

#define CPUOFF (0x0010u)

#define OSCOFF (0x0020u)

#define SCG0 (0x0040u)

#define SCG1 (0x0080u)

/* Low Power Modes coded with Bits 4-7 in SR */

#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */

#define LPM0 (CPUOFF)

#define LPM1 (SCG0+CPUOFF)

#define LPM2 (SCG1+CPUOFF)

#define LPM3 (SCG1+SCG0+CPUOFF)

#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)

/* End #defines for assembler */

#else /* Begin #defines for C */

#define LPM0_bits (CPUOFF)

#define LPM1_bits (SCG0+CPUOFF)

#define LPM2_bits (SCG1+CPUOFF)

#define LPM3_bits (SCG1+SCG0+CPUOFF)

#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)

#include "in430.h"

#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */

#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */

#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */

#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */

#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */

#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */

#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */

#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */

#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */

#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */

#endif /* End #defines for C */

/************************************************************

* PERIPHERAL FILE MAP

************************************************************/

/************************************************************

* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS

************************************************************/

#define IE1_ (0x0000u) /* Interrupt Enable 1 */

DEFC( IE1 , IE1_)

#define U0IE IE1 /* UART0 Interrupt Enable Register */

#define WDTIE (0x01)

#define OFIE (0x02)

#define NMIIE (0x10)

#define ACCVIE (0x20)

#define URXIE0 (0x40)

#define UTXIE0 (0x80)

#define IFG1_ (0x0002u) /* Interrupt Flag 1 */

DEFC( IFG1 , IFG1_)

#define U0IFG IFG1 /* UART0 Interrupt Flag Register */

#define WDTIFG (0x01)

#define OFIFG (0x02)

#define NMIIFG (0x10)

#define URXIFG0 (0x40)

#define UTXIFG0 (0x80)

#define ME1_ (0x0004u) /* Module Enable 1 */

DEFC( ME1 , ME1_)

#define U0ME ME1 /* UART0 Module Enable Register */

#define URXE0 (0x40)

#define UTXE0 (0x80)

#define USPIE0 (0x40)

#define IE2_ (0x0001u) /* Interrupt Enable 2 */

DEFC( IE2 , IE2_)

#define U1IE IE2 /* UART1 Interrupt Enable Register */

#define URXIE1 (0x10)

#define UTXIE1 (0x20)

#define IFG2_ (0x0003u) /* Interrupt Flag 2 */

DEFC( IFG2 , IFG2_)

#define U1IFG IFG2 /* UART1 Interrupt Flag Register */

#define URXIFG1 (0x10)

#define UTXIFG1 (0x20)

#define ME2_ (0x0005u) /* Module Enable 2 */

DEFC( ME2 , ME2_)

#define U1ME ME2 /* UART1 Module Enable Register */

#define URXE1 (0x10)

#define UTXE1 (0x20)

#define USPIE1 (0x10)

/************************************************************

* WATCHDOG TIMER

************************************************************/

#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */

#define WDTCTL_ (0x0120u) /* Watchdog Timer Control */

DEFW( WDTCTL , WDTCTL_)

/* The bit names have been prefixed with "WDT" */

#define WDTIS0 (0x0001u)

#define WDTIS1 (0x0002u)

#define WDTSSEL (0x0004u)

#define WDTCNTCL (0x0008u)

#define WDTTMSEL (0x0010u)

#define WDTNMI (0x0020u)

#define WDTNMIES (0x0040u)

#define WDTHOLD (0x0080u)

#define WDTPW (0x5A00u)

/* WDT-interval times [1ms] coded with Bits 0-2 */

/* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL)

/* 32ms interval (default) */

#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)

/* 8ms " */

#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)

/* 0.5ms " */

#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)

/* 0.064ms " */

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)

/* 1000ms " */

#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)

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