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首页DE2-115 FPGA 原理图
DE2-115 FPGA 原理图
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更新于2023-06-13
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这是台湾TERASIC公司的产品DE2-115的原理图,其包含了液晶、数码管、音频、视频、网络、PS2、串口等各项功能
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
03 DISPLAY 07 ~ 08
SDRAM , SRAM , FLASH , SD CARD
WM8731
Cyclone IV EP4CE115 BANK1..BANK8 , POWER , CONFIG
10 POWER
19
01 TOP 01 ~ 03
15 ~ 16
09 ~ 14
PAGE
21 ~ 25
04 ~ 06
SCHEMATIC
ALTERA Cyclone IV Development & Education Board (DE2-115)
17 ~ 18
CONTENT
Cover Page, Placement,TOP
05 ETHERNET
CLOCK, IrDA, PS2 , RS232 , BUTTON , SWITCH , HSMC, EEPROM
09 FPGA
LCD , LED , 7SEGMENT
08 USB DEVICE 20
02 MEMORY
88E1111
07 AUDIO
ADV7123, ADV718006 VIDEO
04 IN/OUT
ISP1362
POWER 1.2V, 1.8V, 2.5V, 3.3V, 5V 26 ~ 27
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE2-115 Main Board
B
1 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE2-115 Main Board
B
1 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE2-115 Main Board
B
1 27Friday, September 24, 2010
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE2-115 Main Board
B
2 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE2-115 Main Board
B
2 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE2-115 Main Board
B
2 27Friday, September 24, 2010
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DRAM_DQ[31..0]
DRAM_ADDR[12..0]
DRAM_DQM[3..0]
SRAM_DQ[15..0]
SRAM_ADDR[19..0]
FL_DQ[7..0]
FL_ADDR[22..0]
SD_DAT[3..0]
LCD_DATA[7..0]
HEX0[6..0]
HEX1[6..0]
HEX2[6..0]
HEX3[6..0]
HEX4[6..0]
HEX5[6..0]
HEX6[6..0]
HEX7[6..0]
LEDG[8..0]
LEDR[17..0]
SW[17..0]
KEY[3..0]
GPIO[35..0]
HSMC_D[3..0]
HSMC_TX_D_P[16..0]
HSMC_TX_D_N[16..0]
HSMC_RX_D_P[16..0]
HSMC_RX_D_N[16..0]
VGA_B[7..0]
VGA_G[7..0]
VGA_R[7..0]
ENET1_RX_DATA[3..0]
ENET0_TX_DATA[3..0]
ENET0_RX_DATA[3..0]DRAM_DQ[31..0]
SRAM_DQ[15..0]
FL_DQ[7..0]
SD_DAT[3..0]
LCD_DATA[7..0]
GPIO[35..0]
SW[17..0]
KEY[3..0]
HSMC_TX_D_P[16..0]
HSMC_TX_D_N[16..0]
HSMC_RX_D_P[16..0]
HSMC_RX_D_N[16..0]
DRAM_ADDR[12..0]
SRAM_ADDR[19..0]
FL_ADDR[22..0]
LEDR[17..0]
LEDG[8..0]
HEX0[6..0]
HEX1[6..0]
HEX2[6..0]
HEX3[6..0]
HEX4[6..0]
HEX5[6..0]
HEX6[6..0]
HEX7[6..0]
DRAM_BA1
DRAM_CAS_N
DRAM_RAS_N
DRAM_CKE
DRAM_WE_N
DRAM_CS_N
DRAM_CLK
SRAM_UB_N
SRAM_LB_N
SRAM_WE_N
SRAM_OE_N
SRAM_CE_N
FL_WP_N
FL_CE_N
FL_OE_N
FL_WE_N
FL_RST_N
SD_CLK SD_CMD
FL_RY
LCD_ON
LCD_BLON
LCD_EN
LCD_RS
LCD_RW
SMA_CLKOUT CLOCK_50
CLOCK2_50
CLOCK3_50
SMA_CLKIN
PS2_CLK2
PS2_DAT2
PS2_CLK
PS2_DAT
UART_RXD
UART_RTS
IRDA_RXD
EEP_I2C_SDAT
JTAG_TDO
I2C_SDAT
I2C_SCLK
HSMC_CLKOUT0
HSMC_CLKIN_P1
HSMC_CLKIN_N1
HSMC_CLKIN_P2
HSMC_CLKIN_N2
HSMC_CLKIN0
UART_TXD
UART_CTS
EEP_I2C_SCLK
FPGA_TDO
JTAG_TMS
JTAG_TCK
HSMC_CLKOUT_P1
HSMC_CLKOUT_N1
DRAM_CAS_N
DRAM_RAS_N
DRAM_BA0
DRAM_BA1
DRAM_CKE
DRAM_WE_N
DRAM_CS_N
DRAM_CLK
SRAM_CE_N
SRAM_OE_N
SRAM_WE_N
SRAM_UB_N
SRAM_LB_N
FL_RST_N
FL_WE_N
FL_CE_N
FL_WP_N
FL_OE_N
FL_RY
SD_CLK
SD_WP_N
SD_CMD
LCD_ON
LCD_EN
LCD_RW
LCD_RS
LCD_BLON
CLOCK_50
CLOCK2_50
CLOCK3_50
SMA_CLKIN
SMA_CLKOUT
IRDA_RXD
UART_TXD
UART_RXD
UART_RTS
UART_CTS
PS2_CLK
PS2_DAT
PS2_CLK2
PS2_DAT2
HSMC_CLKIN_P1
HSMC_CLKIN_N1
HSMC_CLKIN_P2
HSMC_CLKIN_N2
HSMC_CLKOUT_P1
HSMC_CLKOUT_N1
HSMC_CLKOUT_P2
HSMC_CLKOUT_N2
HSMC_CLKIN0
HSMC_CLKOUT0
ENET0_RX_ER
ENET0_RX_COL
ENET0_RX_CRS
ENET0_RX_DV
ENET0_RX_CLK
ENET0_TX_CLK
ENET0_GTX_CLK
ENET0_TX_EN
ENET0_TX_ER
ENET0_INT_N
ENET0_RST_N
ENET0_MDC
ENET0_MDIO
ENET1_RX_ER
ENET1_RX_COL
ENET1_RX_CRS
ENET1_RX_DV
ENET1_RX_CLK
ENET1_TX_CLK
ENET1_GTX_CLK
ENET1_TX_EN
ENET1_TX_ER
ENET1_INT_N
ENET1_RST_N
ENET1_MDC
ENET1_MDIO
VGA_CLK
AUD_XCK
AUD_BCLK
AUD_ADCDAT
AUD_ADCLRCK
AUD_DACDAT
AUD_DACLRCK
JTAG_TMS
JTAG_TCK
JTAG_TDI
FPGA_TDO
NSTATUS
CONF_DONE
NCONFIG
NCE
DCLK
DATA0
NCSO
ASDO
EEP_I2C_SCLK
EEP_I2C_SDAT
ENET0_TX_DATA[3..0] ENET0_RX_DATA[3..0]
ENET1_TX_DATA[3..0] ENET1_RX_DATA[3..0]
VGA_R[7..0]
VGA_G[7..0]
VGA_B[7..0]
ENET0_RX_DV
ENET0_RX_ER
ENET0_RX_CRS
ENET0_RX_COL
ENET0_RX_CLK
ENET0_TX_CLK
ENET0_INT_N
ENET0_MDIO
ENET0_GTX_CLK
ENET0_TX_EN
ENET0_TX_ER
ENET0_RST_N
ENET0_MDC
ENET1_MDC
ENET1_GTX_CLK
ENET1_TX_EN
ENET1_TX_ER
ENET1_RST_N
ENET1_RX_DV
ENET1_RX_ER
ENET1_RX_CRS
ENET1_RX_COL
ENET1_RX_CLK
ENET1_TX_CLK
ENET1_INT_N
ENET1_MDIO
VGA_SYNC_N
VGA_CLK
VGA_VS
VGA_HS
AUD_ADCDAT
AUD_BCLK
AUD_DACLRCK
AUD_ADCLRCK
AUD_DACDAT
AUD_XCK
I2C_SDAT
I2C_SCLK
DRAM_DQM[3..0]
DRAM_BA0
SD_WP_N
HSMC_D[3..0]
HSMC_CLKOUT_P2
HSMC_CLKOUT_N2
VGA_BLANK_N
TD_RESET_N
TD_DATA[7..0]
TD_VS
TD_HS
TD_CLK27
I2C_SCLK
I2C_SDAT
ENET1_TX_DATA[3..0]
EX_IO[6..0]
EX_IO[6..0]
VGA_BLANK_N
VGA_SYNC_N
VGA_VS
VGA_HS
OTG_DATA[15..0]
OTG_INT1
OTG_INT0
OTG_DREQ1
OTG_DREQ0
OTG_FSPEED
OTG_LSPEED
OTG_DACK_N1
OTG_DACK_N0
OTG_ADDR1
OTG_ADDR0
OTG_RD_N
OTG_WR_N
OTG_CS_N
OTG_RST_N
OTG_DATA[15..0]
OTG_FSPEED
OTG_LSPEED
OTG_INT1
OTG_INT0
OTG_DREQ1
OTG_DREQ0
OTG_ADDR1
OTG_ADDR0
OTG_CS_N
OTG_WR_N
OTG_RD_N
OTG_DACK_N1
OTG_DACK_N0
OTG_RST_N
USB_12MHz
TD_RESET_N
TD_CLK27
TD_HS
TD_VS
TD_DATA[7..0]
I2C_SDAT
I2C_SCLK
ENET1_LINK100
ENETCLK_25
ENET0_LINK100
ENET0_LINK100
ENET1_LINK100
ENETCLK_25
Title
S
ize Document Number Rev
Date: Sheet of
Copyrig ht (c) 200 7 by Terasic Tec hnolog ies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reser ved.
TOP B
DE2-115 Main Board
C
3 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyrig ht (c) 200 7 by Terasic Tec hnolog ies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reser ved.
TOP B
DE2-115 Main Board
C
3 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyrig ht (c) 200 7 by Terasic Tec hnolog ies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reser ved.
TOP B
DE2-115 Main Board
C
3 27Friday, September 24, 2010
PAGE 2008 USB DEVICE
OTG_INT0
OTG_LSPEED
OTG_DATA[15..0]
OTG_INT1
OTG_FSPEED
OTG_DREQ0
OTG_DREQ1
USB_12MHz
OTG_CS_N
OTG_ADDR0
OTG_ADDR1
OTG_RST_N
OTG_DACK_N0
OTG_DACK_N1
OTG_RD_N
OTG_WR_N
PAGE 17-1806 VIDEO
VGA_HS
VGA_VS
VGA_CLK
TD_HS
TD_VS
TD_RESET_n
TD_CLK27
TD_DATA[7..0]
VGA_G[7..0]
VGA_R[7..0]
VGA_B[7..0]
VGA_BLANK_N
VGA_SYNC_N
I2C_SDAT
I2C_SCLK
PAGE 15-1605 ETHERNET
ENET0_GTX_CLK
ENET1_TX_ER
ENET0_RX_CLK
ENET1_MDIO
ENET0_MDIO
ENET0_MDC
ENET1_TX_DATA[3..0]
ENET0_RX_DV
ENET0_RX_CRS
ENET1_RX_DV
ENET1_LINK100
ENET1_MDC
ENET0_TX_EN
ENET1_TX_EN
ENET1_GTX_CLK
ENET0_TX_DATA[3..0]
ENET0_TX_ER
ENET0_RX_DATA[3..0]
ENET1_TX_CLK
ENET1_RX_COL
ENETCLK_25
ENET1_RX_CLK
ENET0_LINK100
ENET0_INT_N
ENET1_INT_N
ENET1_RX_CRS
ENET1_RX_DATA[3..0]
ENET0_RX_ER
ENET1_RX_ER
ENET0_TX_CLK
ENET0_RX_COLENET0_RST_N
ENET1_RST_N
PAGE 9 - 1404 IN/OUT
HSMC_TDI
HSMC_CLKIN0
HSMC_CLKOUT0
HSMC_SCL
HSMC_SDAHSMC_TMS
HSMC_TCK
UART_TXD UART_RXD
JTAG_TDO
SW[17..0]
KEY[3..0]
UART_CTS
SMA_CLKOUT
UART_RTS
SMA_CLKIN
IRDA_RXD
HSMC_D[3..0]
EX_IO[6..0]
CLOCK_50
CLOCK3_50
CLOCK2_50
HSMC_CLKIN_P1
HSMC_CLKIN_P2
HSMC_CLKIN_N1
HSMC_CLKIN_N2
HSMC_CLKOUT_P1
HSMC_CLKOUT_P2
HSMC_CLKOUT_N1
HSMC_CLKOUT_N2
HSMC_TX_D_P[16..0]
HSMC_TX_D_N[16..0]
HSMC_RX_D_P[16..0]
HSMC_RX_D_N[16..0]
GPIO[35..0]
PS2_DAT2
PS2_CLK
PS2_CLK2
PS2_DAT
EEP_I2C_SCLK EEP_I2C_SDAT
PAGE 7-803 DISPLAY
LCD_BLON
LCD_ON
LCD_EN
LCD_RS
LCD_RW
LEDG[8..0]
LEDR[17..0]
LCD_DATA[7..0]
HEX1[6..0]
HEX2[6..0]
HEX4[6..0]
HEX3[6..0]
HEX5[6..0]
HEX7[6..0]
HEX6[6..0]
HEX0[6..0]
PAGE 1907 AUDIO
AUD_BCLK
AUD_DACLRCK
AUD_ADCLRCK
AUD_DACDAT
AUD_XCK
AUD_ADCDAT
I2C_SDAT
I2C_SCLK
PAGE 26 -2711 POWER
PAGE 21-2510 EP4CE115
DRAM_BA0
DRAM_BA1
DRAM_CLK
DRAM_CKE
LCD_ON
LCD_BLON
LCD_RS
NCSO
DATA0
DRAM_DQ[31..0]
LCD_DATA[7..0]
SRAM_DQ[15..0]
NSTATUS
NCONFIG
LCD_RW
DRAM_DQM[3..0]
IRDA_RXD
SRAM_ADDR[19..0]
SD_CLK
SD_DAT[3..0]
CONF_DONE
DRAM_ADDR[12..0]
LCD_EN
ASDO
NCE
DCLK
SD_CMD
SW[17..0]
LEDG[8..0]
HSMC_CLKOUT0
UART_RXD
UART_RTS
UART_TXD
HSMC_D[3..0]
UART_CTS
SMA_CLKOUT
LEDR[17..0]
SMA_CLKIN
HSMC_CLKIN0
KEY[3..0]
AUD_DACDAT
AUD_ADCLRCK
AUD_ADCDAT
AUD_BCLK
TDO
AUD_DACLRCK
AUD_XCK
VGA_CLK
VGA_HS
VGA_VS
TDI
TMS
TCK
EX_IO[6..0]
OTG_DATA[15..0]
OTG_LSPEED
TD_HS
OTG_INT0
OTG_INT1
TD_VS
OTG_FSPEED
TD_CLK27
OTG_DREQ0
OTG_DREQ1
TD_DATA[7..0]
VGA_G[7..0]
VGA_R[7..0]
VGA_B[7..0]
HEX1[6..0]
HEX2[6..0]
HEX4[6..0]
HEX3[6..0]
HEX5[6..0]
HEX6[6..0]
HEX7[6..0]
HEX0[6..0]
CLOCK_50
CLOCK3_50
CLOCK2_50
HSMC_CLKIN_P1
HSMC_CLKIN_P2
HSMC_CLKIN_N1
HSMC_CLKIN_N2
HSMC_CLKOUT_P1
HSMC_CLKOUT_P2
HSMC_CLKOUT_N1
HSMC_CLKOUT_N2
HSMC_TX_D_P[16..0]
HSMC_TX_D_N[16..0]
HSMC_RX_D_P[16..0]
HSMC_RX_D_N[16..0]
GPIO[35..0]
VGA_BLANK_N
VGA_SYNC_N
I2C_SDAT
I2C_SCLK
PS2_DAT2
PS2_CLK
PS2_CLK2
PS2_DAT
ENET0_GTX_CLK
ENET1_TX_ER
ENET0_RX_CLK
ENET1_MDIO
ENET0_RX_DV
ENET0_MDC
ENET0_MDIO
ENET1_RX_DV
ENET0_RX_CRS
ENET1_LINK100
ENET1_TX_CLK
ENET1_RX_COL
ENET0_RX_DATA[3..0]
ENETCLK_25
ENET1_RX_CLK
ENET0_INT_N
ENET0_LINK100
ENET1_TX_DATA[3..0]
ENET1_MDC
ENET0_TX_EN
ENET1_TX_EN
ENET1_GTX_CLK
ENET0_TX_ER
ENET0_TX_DATA[3..0]
ENET1_INT_N
ENET1_RX_CRS
ENET1_RX_DATA[3..0]
ENET0_RX_ER
ENET1_RX_ER
ENET0_TX_CLK
ENET0_RX_COL
TD_RESET_N
OTG_CS_N
OTG_ADDR0
OTG_ADDR1
SRAM_UB_N
SRAM_WE_N
SRAM_CE_N
SRAM_OE_N
SRAM_LB_N
FL_CE_N
FL_ADDR[22..0]
FL_OE_N
FL_DQ[7..0]
FL_WP_N
FL_RY
FL_WE_N
EEP_I2C_SCLK
EEP_I2C_SDAT
SD_WP_N
OTG_RST_N
OTG_DACK_N0
OTG_DACK_N1
DRAM_CAS_N
DRAM_WE_N
DRAM_CS_N
DRAM_RAS_N
OTG_RD_N
OTG_WR_N
ENET0_RST_N
ENET1_RST_N
FL_RST_N
PAGE 4-602 MEMORY
SD_CMDSD_CLK
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_DQM[3..0]
SD_DAT[3..0]
DRAM_DQ[31..0]
SRAM_DQ[15..0]
SRAM_ADDR[19..0]
DRAM_ADDR[12..0]
SRAM_UB_N
SRAM_WE_N
SRAM_CE_N
SRAM_LB_N
SRAM_OE_N
FL_CE_N
FL_ADDR[22..0]
FL_OE_N
FL_DQ[7..0]FL_WP_N
FL_WE_N FL_RY
SD_WP_N
DRAM_CAS_N
DRAM_CS_N
DRAM_WE_N
DRAM_RAS_N
FL_RST_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDRAM0 SDRAM1
DRAM_DQM2
DRAM_DQM3
DRAM_CKE
DRAM_CAS_N
DRAM_RAS_N
DRAM_CS_N
DRAM_WE_N
DRAM_ADDR3
DRAM_ADDR0
DRAM_ADDR2
DRAM_ADDR1
DRAM_ADDR10
DRAM_DQM0
DRAM_DQ5
DRAM_DQ0
DRAM_DQ7
DRAM_DQ6
DRAM_DQ3
DRAM_DQ2
DRAM_DQ4
DRAM_DQ1
DRAM_ADDR3
DRAM_ADDR0
DRAM_ADDR2
DRAM_ADDR1
DRAM_ADDR10
DRAM_DQ21
DRAM_DQ16
DRAM_DQ23
DRAM_DQ22
DRAM_DQ19
DRAM_DQ18
DRAM_DQ20
DRAM_DQ17
DRAM_ADDR12
DRAM_ADDR5
DRAM_ADDR7
DRAM_ADDR6
DRAM_ADDR8
DRAM_ADDR11
DRAM_ADDR4
DRAM_ADDR9
DRAM_DQ24
DRAM_DQ31
DRAM_DQ27
DRAM_DQ25
DRAM_DQ26
DRAM_DQ29
DRAM_DQ30
DRAM_DQ28DRAM_ADDR12
DRAM_ADDR5
DRAM_ADDR7
DRAM_ADDR6
DRAM_ADDR8
DRAM_ADDR11
DRAM_ADDR4
DRAM_ADDR9
DRAM_DQM1
DRAM_DQ8
DRAM_DQ15
DRAM_DQ11
DRAM_DQ9
DRAM_DQ10
DRAM_DQ13
DRAM_DQ14
DRAM_DQ12
DRAM_CLK
DRAM_CKE
DRAM_WE_n
DRAM_CAS_n
DRAM_RAS_n
DRAM_CS_n
DRAM_BA0
DRAM_BA1
DRAM_DQ[31..0]
DRAM_ADDR[12..0]
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_WE_N
DRAM_CAS_N
DRAM_RAS_N
DRAM_CS_N
DRAM_DQM[3..0]
DR_VCC3P3 DR_VCC3P3 DR_VCC3P3
DR_VCC3P3
DR_VCC3P3DR_VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE2-115 Main Board
A
4 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE2-115 Main Board
A
4 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE2-115 Main Board
A
4 27Friday, September 24, 2010
C287
0.1u
C284
0.1u
C281
0.1u
C282
0.1u
U13
SDRAM 32Mx16
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
nCAS
17
nRAS
18
LDQM
15
nWE
16
nCS
19
CKE
37
CLK
38
UDQM
39
D0
2
D1
4
D2
5
D3
7
D4
8
D5
10
D6
11
D7
13
D8
42
D9
44
D10
45
D11
47
D12
48
D13
50
D14
51
D15
53
A12
36
BA0
20
VDD
1
VDD
27
VSS
28
VSS
41
A10
22
VDDQ
3
VDDQ
9
VDDQ
43
VDDQ
49
VSSQ
6
VSSQ
12
VSSQ
46
VSSQ
52
A11
35
BA1
21
VSS
54
VDD
14
R223 4.7K
C85
10u
R224 4.7K
U15
SDRAM 32Mx16
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
nCAS
17
nRAS
18
LDQM
15
nWE
16
nCS
19
CKE
37
CLK
38
UDQM
39
D0
2
D1
4
D2
5
D3
7
D4
8
D5
10
D6
11
D7
13
D8
42
D9
44
D10
45
D11
47
D12
48
D13
50
D14
51
D15
53
A12
36
BA0
20
VDD
1
VDD
27
VSS
28
VSS
41
A10
22
VDDQ
3
VDDQ
9
VDDQ
43
VDDQ
49
VSSQ
6
VSSQ
12
VSSQ
46
VSSQ
52
A11
35
BA1
21
VSS
54
VDD
14
R226 4.7K
R225 4.7K
C286
0.1u
C260
0.1u
C272
0.1u
C258
0.1u
C261
0.1u
C259
0.1u
C280
0.1u
C283
0.1u
R235 0
R234 4.7K
C262
0.1u
C273
0.1u
C82
10u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SRAM_ADDR19
SRAM_ADDR18
SRAM_ADDR17
SRAM_ADDR16
SRAM_ADDR15
SRAM_ADDR14
SRAM_ADDR13
SRAM_ADDR12
SRAM_ADDR11
SRAM_ADDR10
SRAM_ADDR7
SRAM_ADDR6
SRAM_ADDR5
SRAM_ADDR4
SRAM_ADDR3
SRAM_ADDR2
SRAM_ADDR1
SRAM_ADDR0
SRAM_DQ0
SRAM_DQ1
SRAM_DQ2
SRAM_DQ3
SRAM_DQ4
SRAM_DQ5
SRAM_DQ6
SRAM_DQ7
SRAM_DQ8
SRAM_DQ9
SRAM_DQ10
SRAM_DQ11
SRAM_DQ12
SRAM_DQ13
SRAM_DQ14
SRAM_DQ15
SRAM_ADDR8
SRAM_ADDR9
SRAM_CE_N
SRAM_DQ[15..0]
SRAM_ADDR[19..0]
SRAM_CE_N
SRAM_OE_N
SRAM_WE_N
SRAM_UB_N
SRAM_LB_N
SR_VCC3P3
VCC3P3
SR_VCC3P3
SR_VCC3P3
SR_VCC3P3
Title
Size Document Number Rev
Date: Sheet
of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SRAM B
DE2-115 Main Board
A
5 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SRAM B
DE2-115 Main Board
A
5 27Friday, September 24, 2010
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SRAM B
DE2-115 Main Board
A
5 27Friday, September 24, 2010
C289
0.1u
U17
SRAM 1Mx16
A0
5
A1
4
A2
3
A3
2
A4
1
A5
48
A6
47
A7
46
A8
45
A9
30
A10
29
A11
28
A12
27
A13
26
A14
25
A15
24
A16
23
A17
22
A18
21
A19
20
I/O0
8
I/O1
9
I/O2
10
I/O3
11
I/O4
14
I/O5
15
I/O6
16
I/O7
17
I/O8
32
I/O9
33
I/O10
34
I/O11
35
I/O12
38
I/O13
39
I/O14
40
I/O15
41
CE_n
7
WE_n
18
OE_n
44
UB_n
43
LB_n
42
VDD
12
VDD
36
GND
13
GND
37
NC1
6
NC2
19
NC3
31
C290
0.1u
R78 0
R240 4.7K
C86
10u
剩余26页未读,继续阅读
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