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NVM Express 1.1

NVM Express

Revision 1.1

October 11, 2012

Please send comments to Amber Huffman

amber.huffman@intel.com

NVM Express 1.1

Table of Contents

1 INTRODUCTION ............................................................................................................. 8

1.1 Overview ......................................................................................................................................... 8

1.2 Scope .............................................................................................................................................. 8

1.3 Outside of Scope ............................................................................................................................ 8

1.4 Theory of Operation ........................................................................................................................ 8

1.4.1 Multi-Path I/O and Namespace Sharing ............................................................................................... 10

1.5 Conventions .................................................................................................................................. 13

1.6 Definitions ..................................................................................................................................... 14

1.6.1 Admin Queue ....................................................................................................................................... 14

1.6.2 arbitration burst .................................................................................................................................... 14

1.6.3 arbitration mechanism .......................................................................................................................... 14

1.6.4 candidate command ............................................................................................................................. 14

1.6.5 command completion ........................................................................................................................... 14

1.6.6 command submission ........................................................................................................................... 14

1.6.7 controller .............................................................................................................................................. 14

1.6.8 extended LBA ....................................................................................................................................... 14

1.6.9 firmware slot ......................................................................................................................................... 14

1.6.10 I/O command ........................................................................................................................................ 14

1.6.11 I/O Completion Queue .......................................................................................................................... 14

1.6.12 I/O Submission Queue ......................................................................................................................... 14

1.6.13 LBA range ............................................................................................................................................ 15

1.6.14 logical block .......................................................................................................................................... 15

1.6.15 logical block address (LBA) .................................................................................................................. 15

1.6.16 metadata .............................................................................................................................................. 15

1.6.17 namespace ........................................................................................................................................... 15

1.6.18 Namespace ID...................................................................................................................................... 15

1.6.19 NVM ..................................................................................................................................................... 15

1.6.20 NVM subsystem ................................................................................................................................... 15

1.6.21 private namespace ............................................................................................................................... 15

1.6.22 shared namespace ............................................................................................................................... 15

1.7 Keywords ...................................................................................................................................... 15

1.7.1 mandatory ............................................................................................................................................ 15

1.7.2 may ...................................................................................................................................................... 15

1.7.3 optional ................................................................................................................................................. 16

1.7.4 R ........................................................................................................................................................... 16

1.7.5 reserved ............................................................................................................................................... 16

1.7.6 shall ...................................................................................................................................................... 16

1.7.7 should ................................................................................................................................................... 16

1.8 Conventions .................................................................................................................................. 16

1.9 Byte, word and Dword Relationships ............................................................................................ 17

1.10 References ................................................................................................................................ 17

1.11 References Under Development ............................................................................................... 18

2 SYSTEM BUS (PCI EXPRESS) REGISTERS ....................................................................... 19

2.1 PCI Header ................................................................................................................................... 19

2.1.1 Offset 00h: ID - Identifiers .................................................................................................................... 20

2.1.2 Offset 04h: CMD - Command ............................................................................................................... 20

2.1.3 Offset 06h: STS - Device Status........................................................................................................... 20

2.1.4 Offset 08h: RID - Revision ID ............................................................................................................... 20

2.1.5 Offset 09h: CC - Class Code ................................................................................................................ 21

2.1.6 Offset 0Ch: CLS – Cache Line Size ..................................................................................................... 21

2.1.7 Offset 0Dh: MLT – Master Latency Timer ............................................................................................ 21

2.1.8 Offset 0Eh: HTYPE – Header Type ...................................................................................................... 21

2.1.9 Offset 0Fh: BIST – Built In Self Test (Optional) .................................................................................... 21

2.1.10 Offset 10h: MLBAR (BAR0) – Memory Register Base Address, lower 32-bits ..................................... 21

2.1.11 Offset 14h: MUBAR (BAR1) – Memory Register Base Address, upper 32-bits .................................... 22

2.1.12 Offset 18h: IDBAR (BAR2) – Index/Data Pair Register Base Address (Optional) ................................ 22

NVM Express 1.1

2.1.13 Offset 1Ch – 20h: BAR3 –Reserved..................................................................................................... 22

2.1.14 Offset 20h – 23h: BAR4 – Vendor Specific .......................................................................................... 22

2.1.15 Offset 24h – 27h: BAR5 – Vendor Specific .......................................................................................... 22

2.1.16 Offset 28h: CCPTR – CardBus CIS Pointer ......................................................................................... 22

2.1.17 Offset 2Ch: SS - Sub System Identifiers .............................................................................................. 22

2.1.18 Offset 30h: EROM – Expansion ROM (Optional) ................................................................................. 22

2.1.19 Offset 34h: CAP – Capabilities Pointer ................................................................................................. 22

2.1.20 Offset 3Ch: INTR - Interrupt Information .............................................................................................. 23

2.1.21 Offset 3Eh: MGNT – Minimum Grant ................................................................................................... 23

2.1.22 Offset 3Fh: MLAT – Maximum Latency ................................................................................................ 23

2.2 PCI Power Management Capabilities ........................................................................................... 23

2.2.1 Offset PMCAP: PID - PCI Power Management Capability ID ............................................................... 23

2.2.2 Offset PMCAP + 2h: PC – PCI Power Management Capabilities ......................................................... 23

2.2.3 Offset PMCAP + 4h: PMCS – PCI Power Management Control and Status ........................................ 24

2.3 Message Signaled Interrupt Capability (Optional) ........................................................................ 24

2.3.1 Offset MSICAP: MID – Message Signaled Interrupt Identifiers ............................................................ 24

2.3.2 Offset MSICAP + 2h: MC – Message Signaled Interrupt Message Control .......................................... 24

2.3.3 Offset MSICAP + 4h: MA – Message Signaled Interrupt Message Address ........................................ 25

2.3.4 Offset MSICAP + 8h: MUA – Message Signaled Interrupt Upper Address........................................... 25

2.3.5 Offset MSICAP + Ch: MD – Message Signaled Interrupt Message Data ............................................. 25

2.3.6 Offset MSICAP + 10h: MMASK – Message Signaled Interrupt Mask Bits (Optional) ........................... 25

2.3.7 Offset MSICAP + 14h: MPEND – Message Signaled Interrupt Pending Bits (Optional) ....................... 25

2.4 MSI-X Capability (Optional) .......................................................................................................... 25

2.4.1 Offset MSIXCAP: MXID – MSI-X Identifiers ......................................................................................... 25

2.4.2 Offset MSIXCAP + 2h: MXC – MSI-X Message Control ....................................................................... 26

2.4.3 Offset MSIXCAP + 4h: MTAB – MSI-X Table Offset / Table BIR ......................................................... 26

2.4.4 Offset MSIXCAP + 8h: MPBA – MSI-X PBA Offset / PBA BIR ............................................................. 26

2.5 PCI Express Capability (Optional) ................................................................................................ 27

2.5.1 Offset PXCAP: PXID – PCI Express Capability ID ............................................................................... 27

2.5.2 Offset PXCAP + 2h: PXCAP – PCI Express Capabilities ..................................................................... 27

2.5.3 Offset PXCAP + 4h: PXDCAP – PCI Express Device Capabilities ....................................................... 27

2.5.4 Offset PXCAP + 8h: PXDC – PCI Express Device Control .................................................................. 28

2.5.5 Offset PXCAP + Ah: PXDS – PCI Express Device Status.................................................................... 29

2.5.6 Offset PXCAP + Ch: PXLCAP – PCI Express Link Capabilities ........................................................... 29

2.5.7 Offset PXCAP + 10h: PXLC – PCI Express Link Control ..................................................................... 30

2.5.8 Offset PXCAP + 12h: PXLS – PCI Express Link Status ....................................................................... 30

2.5.9 Offset PXCAP + 24h: PXDCAP2 – PCI Express Device Capabilities 2 ................................................ 30

2.5.10 Offset PXCAP + 28h: PXDC2 – PCI Express Device Control 2 ........................................................... 31

2.6 Advanced Error Reporting Capability (Optional) .......................................................................... 31

2.6.1 Offset AERCAP: AERID – AER Capability ID ...................................................................................... 32

2.6.2 Offset AERCAP + 4: AERUCES – AER Uncorrectable Error Status Register ...................................... 32

2.6.3 Offset AERCAP + 8: AERUCEM – AER Uncorrectable Error Mask Register ....................................... 32

2.6.4 Offset AERCAP + Ch: AERUCESEV – AER Uncorrectable Error Severity Register ............................ 33

2.6.5 Offset AERCAP + 10h: AERCS – AER Correctable Error Status Register........................................... 33

2.6.6 Offset AERCAP + 14h: AERCEM – AER Correctable Error Mask Register ......................................... 34

2.6.7 Offset AERCAP + 18h: AERCC – AER Capabilities and Control Register ........................................... 34

2.6.8 Offset AERCAP + 1Ch: AERHL – AER Header Log Register .............................................................. 35

2.6.9 Offset AERCAP + 38h: AERTLP – AER TLP Prefix Log Register (Optional) ....................................... 35

2.7 Other Capability Pointers .............................................................................................................. 35

3 CONTROLLER REGISTERS ............................................................................................. 36

3.1 Register Definition ........................................................................................................................ 36

3.1.1 Offset 00h: CAP – Controller Capabilities ............................................................................................ 37

3.1.2 Offset 08h: VS – Version ...................................................................................................................... 38

3.1.3 Offset 0Ch: INTMS – Interrupt Mask Set .............................................................................................. 38

3.1.4 Offset 10h: INTMC – Interrupt Mask Clear ........................................................................................... 38

3.1.5 Offset 14h: CC – Controller Configuration ............................................................................................ 38

3.1.6 Offset 1Ch: CSTS – Controller Status .................................................................................................. 40

3.1.7 Offset 20h: NSSR – NVM Subsystem Reset ........................................................................................ 41

3.1.8 Offset 24h: AQA – Admin Queue Attributes ......................................................................................... 41

3.1.9 Offset 28h: ASQ – Admin Submission Queue Base Address ............................................................... 41

NVM Express 1.1

3.1.10 Offset 30h: ACQ – Admin Completion Queue Base Address ............................................................... 42

3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL – Submission Queue y Tail Doorbell ........... 42

3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL – Completion Queue y Head Doorbell .. 42

3.2 Index/Data Pair registers (Optional) ............................................................................................. 42

3.2.1 Restrictions .......................................................................................................................................... 43

3.2.2 Register Definition ................................................................................................................................ 43

3.2.3 Offset 00h: IDX – Index Register .......................................................................................................... 43

3.2.4 Offset 04h: DAT – Data Register .......................................................................................................... 43

4 SYSTEM MEMORY STRUCTURES .................................................................................... 44

4.1 Submission Queue & Completion Queue Definition ..................................................................... 44

4.1.1 Empty Queue ....................................................................................................................................... 45

4.1.2 Full Queue ............................................................................................................................................ 45

4.1.3 Queue Size .......................................................................................................................................... 45

4.1.4 Queue Identifier .................................................................................................................................... 46

4.1.5 Queue Priority ...................................................................................................................................... 46

4.2 Submission Queue Entry – Command Format ............................................................................. 46

4.3 Physical Region Page Entry and List ........................................................................................... 49

4.4 Scatter Gather List (SGL) ............................................................................................................. 50

4.4.1 SGL Example ....................................................................................................................................... 53

4.5 Metadata Region (MR) ................................................................................................................. 55

4.6 Completion Queue Entry .............................................................................................................. 55

4.6.1 Status Field Definition .......................................................................................................................... 56

4.7 Fused Operations ......................................................................................................................... 60

4.8 Command Arbitration .................................................................................................................... 60

4.8.1 Round Robin Arbitration ....................................................................................................................... 61

4.8.2 Weighted Round Robin with Urgent Priority Class Arbitration .............................................................. 61

4.8.3 Vendor Specific Arbitration ................................................................................................................... 63

5 ADMIN COMMAND SET ................................................................................................. 64

5.1 Abort command ............................................................................................................................ 65

5.1.1 Command Completion .......................................................................................................................... 65

5.2 Asynchronous Event Request command ..................................................................................... 66

5.2.1 Command Completion .......................................................................................................................... 66

5.3 Create I/O Completion Queue command ..................................................................................... 68

5.3.1 Command Completion .......................................................................................................................... 69

5.4 Create I/O Submission Queue command ..................................................................................... 69

5.4.1 Command Completion .......................................................................................................................... 70

5.5 Delete I/O Completion Queue command ..................................................................................... 71

5.5.1 Command Completion .......................................................................................................................... 71

5.6 Delete I/O Submission Queue command ..................................................................................... 71

5.6.1 Command Completion .......................................................................................................................... 72

5.7 Firmware Activate command ........................................................................................................ 72

5.7.1 Command Completion .......................................................................................................................... 73

5.8 Firmware Image Download command .......................................................................................... 73

5.8.1 Command Completion .......................................................................................................................... 74

5.9 Get Features command ................................................................................................................ 74

5.9.1 Select field ............................................................................................................................................ 75

5.9.2 Command Completion .......................................................................................................................... 76

5.10 Get Log Page command ........................................................................................................... 76

5.10.1 Log Specific Information ....................................................................................................................... 77

5.10.1.4.1 Reservation Notification (Log Identifier 80h) ................................................................................ 81

5.10.2 Command Completion .......................................................................................................................... 82

5.11 Identify command ...................................................................................................................... 82

5.11.1 Command Completion .......................................................................................................................... 94

5.12 Set Features command ............................................................................................................. 94

5.12.1 Feature Specific Information ................................................................................................................ 95

5.12.2 Command Completion ........................................................................................................................ 105

5.13 Format NVM command – NVM Command Set Specific ......................................................... 105