Verilog SDRAM模型：兼容多种容量与特性

verilog

SDRAM

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Table 4: Pin and Ball Descriptions

Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides precharge power-down and SELF REFRESH operation (all banks idle), active pow-

er-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress).

CKE is synchronous except after the device enters power-down and self refresh modes, where

CKE becomes asynchronous until after exiting the same mode. The input buffers, including

CLK, are disabled during power-down and self refresh modes, providing low standby power.

CKE may be tied HIGH.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decod-

er. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in

progress will continue, and DQM operation will retain its DQ mask capability while CS# is

HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-

ered part of the command code.

CAS#, RAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

x4, x8:

DQM

x16:

DQML, DQMH

LDQM, UDQM

(54-ball)

Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and

an output enable signal for read accesses. Input data is masked during a WRITE cycle. The

output buffers are High-Z (two-clock latency) during a READ cycle. LDQM corresponds to

DQ[7:0], and UDQM corresponds to DQ[15:8]. LDQM and UDQM are considered same-state

when referenced as DQM.

BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE

command is being applied.

A[12:0] Input Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and

READ or WRITE command (column address A[9:0] and A11 for x4; A[9:0] for x8; A[8:0] for x16;

with A10 defining auto precharge) to select one location out of the memory array in the re-

spective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to

be precharged (A10 HIGH) or bank selected by BA[1:0] (LOW). The address inputs also provide

the op-code during a LOAD MODE REGISTER command.

x16:

DQ[15:0]

I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, 45, 48, and 51 are NC for x8; and

pins 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NC for x4).

x8:

DQ[7:0]

I/O Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4).

x4:

DQ[3:0]

I/O Data input/output: Data bus for x4.

DDQ

Supply DQ power: DQ power to the die for improved noise immunity.

SSQ

Supply DQ ground: DQ power to the die for improved noise immunity.

Supply Power supply: +3.3V ±0.3V.

Supply Ground.

–

These should be left unconnected. For x4 and x8 parts, G1 is a no connect, but may be used as

A12 in future designs.

256Mb: x4, x8, x16 SDRAM

Pin and Ball Assignments and Descriptions

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. N 1/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Temperature and Thermal Impedance

It is imperative that the SDRAM device’s temperature specifications, shown in Table 5

(page 19), be maintained to ensure the junction temperature is in the proper operat-

ing range to meet data sheet specifications. An important step in maintaining the

proper junction temperature is using the device’s thermal impedances correctly. The

thermal impedances are listed in Table 6 (page 20) for the applicable die revision and

packages being made available. These thermal impedance values vary according to the

density, package, and particular design used for each device.

Incorrectly using thermal impedances can produce significant errors. Read Micron tech-

nical note TN-00-08, “Thermal Applications” prior to using the thermal impedances

listed in Table 6 (page 20). To ensure the compatibility of current and future designs,

contact Micron Applications Engineering to confirm thermal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the T

specification is not exceeded. In applications where the device’s ambient temperature

is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-

perature specifications.

Table 5: Temperature Limits

Parameter Symbol Min Max Unit Notes

Operating case temperature Commercial T

0 80 °C 1, 2, 3, 4

Industrial –40 90

Automotive –40 105

Junction temperature Commercial T

0 85 °C 3

Industrial –40 95

Automotive –40 110

Ambient temperature Commercial T

0 70 °C 3, 5

Industrial –40 85

Automotive –40 105

Peak reflow temperature T

PEAK

–

260 °C

Notes:

1. MAX operating case temperature, TC, is measured in the center of the package on the

top side of the device, as shown in Figure 10 (page 20), Figure 11 (page 21), and Fig-

ure 12 (page 21).

2. Device functionality is not guaranteed if the device exceeds maximum T

during operation.

3. All temperature specifications must be satisfied.

4. The case temperature should be measured by gluing a thermocouple to the top-center

of the component. This should be done with a 1mm bead of conductive epoxy, as de-

fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple

bead is touching the case.

5. Operating ambient temperature surrounding the package.

256Mb: x4, x8, x16 SDRAM

Temperature and Thermal Impedance

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. N 1/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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