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interrupt and communications controllers, and counter/timers. The chip also incorpo-
rates system resources such as the boot ROM, shared on-chip RAM, a watchdog timer,
a system controller, and an Ethernet interface. Cores also have access to a shared
1Gbit off-die SDRAM, typically accessed through DMA operations.
One of the processing cores is set aside for system management functions and the
rest are used for applications. The choice of this core (the monitor core) is made during
the boot-up process to ensure that no single core failure can compromise the node, and
can be different every time. Therefore, all cores must have symmetric access to all
resources, as shown in the figure.
The GALS system is supported by two separate and different asynchronous
NoCs: a light-weight, packet-switched communications NoC that allows system-wide
inter-processor communication and a system NoC that allows processor access to
chip-wide shared resources. The communications NoC, which has been described
elsewhere [Plana et al. 2008], is shown in the top half of Figure 2, and is built around
a multicast router specifically designed for SpiNNkaker. This NoC extends off-chip to
provide system-wide interprocessor communication. The system NoC is shown in the
lower half of the figure. The design and implementation of this network-on-chip are
described in the following sections.
3. THE SYSTEM NETWORK-ON-CHIP
The system NoC, shown in Figure 3 is the interconnect that provides access to all
shared resources, such as off-die SDRAM, on-chip shared RAM and the system con-
troller. It replaces a conventional on-chip bus, in this case with 19 bus masters (18
ARM cores and the multicast router) and many bus slaves.
The figure highlights the different clock domains that constitute the GALS SoC.
Five different clock sources are distributed across the chip: white and black core
clocks, as well as memory, router, and system clocks. The cores are divided into two
mesochronous sets physically distributed in a checkerboard pattern. The clock phases
to every core in a set have been purposely skewed to distribute activity more evenly in
time. The network targets have been classified according to their bandwidth require-
ments and the fabric has been optimized accordingly.
3.1. Requirements
Cores have local private resources such as program and data memories, communica-
tion and DMA controllers, and timers. For high-performance operation, application
programs and data are expected to reside in this tightly-coupled memory local on ev-
ery processor. In some cases, such as large neural net simulations, not all data will fit
in local memory; in this case, data will be stored in SDRAM and sections of local mem-
ory can be used as caches. Data transfers between SDRAM are time-critical and are
expected to be done using high-bandwidth DMA operations. On the other hand, shared
on-chip system resources are usually used for boot-up and interprocessor communica-
tion, which are less demanding. As a result, system NoC requirements are relatively
straightforward.
— Given that cores have no predefined assignments or tasks, all should have the same
access to system resources.
— Most of the cores will be devoted to neuron simulation tasks, and therefore, should
have a fair share of network bandwidth.
— SDRAM is the only high-bandwidth target in the system NoC and efficient access
is the key requirement. The NoC must ensure that low- and medium-bandwidth
peripherals interfere as little as possible with SDRAM data bursts.
ACM Journal on Emerging Technologies in Computing Systems, Vol. 7, No. 4, Article 17, Publication date: December 2011.