![](https://csdnimg.cn/release/download_crawler_static/11009148/bg10.jpg)
loginid=harryxu@southbase.cn,time=2018-02-01 10:01:58,ip=183.14.133.140,doctitle=MT2625_Datasheet.pdf,company=
MediaTek MT2625 Datasheet
© 2015 - 2018 MediaTek Inc.
Page 13 of 85
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
2.3.4. Serial Peripheral Interface (SPI)
MT2625 chipset features two SPI master controller and one SPI slave controller to receive and transmit device data
using single, dual and quad SPI protocol. The SPI controllers can communicate at up to 52 Mbps.
The chip select signal and SPI clock of SPI master controllers are configurable. The SPI controllers also support DMA
mode for large amount of data transmission.
2.3.5. Universal Asynchronous Receiver Transmitter (UART)
MT2625 chipset houses four UART interfaces that provide full duplex serial communication between the baseband
chipset and external devices. UART has both M16C450 and M16550A modes of operation compatible with a range
of standard software drivers.
UARTs support baud rates from 110bps up to 3Mbps and baud rate auto-detection function. Both UART1 and
UART2 provide hardware and software flow control of the RTS/CTS signals.
UARTs can configure data transfer lengths from 5 to 8 bits, with an optional parity bit and one or two stop bits by
software. They can be served by the DMA controller.
2.3.6. Inter-Integrated Circuit Interface (I2C)
MT2625 chipset provides two I2C master controllers. There are three types of speed modes in the I2C controllers:
standard mode (100kbit/s), fast mode (400kbit/s) and high-speed mode (3.4Mbit/s), supporting 7-bit/10-bit
addressing and can be served by the DMA controller.
The I2C package size supports up to 1,024 bytes per transfer and 1,024 transfers per transaction in DMA mode and
8 bytes per transfer in non-DMA mode. START, STOP, REPEATED START conditions can be increased to support
single or multiple transfer. These features can be configured by software based on customer requirements.
2.3.7. Pulse-Width Modulation (PWM)
There are four PWM controllers to generate pulse signals. The duty cycle, high time and low time of pulse signals
can be programmed. The PWM controllers can be configured to use 48MHz, 13MHz or 32kHz clock source to
support a wide range of output pulse frequencies.
2.3.8. Keypad Scanner
MT2625 platform provides a keypad hardware module. The keypad supports two types of keypads: 3 x 3 single
keys and 3 x 3 configurable double keys.
The 3 x 3 keypad supports a matrix with 3*3*2 = 18 keys. The 18 keys are divided into 9 subgroups and each group
consists of two keys and a 20Ω resistor. The keypad de-bounce time is software configurable.
2.3.9. DMA
MT2625 chipset features two DMA controllers, containing 27 channels in power down domain. They manage data
transfer between peripheral devices and memory.
There are three types of DMA channels in the DMA controller − full-size DMA channel, half-size DMA channel and
virtual FIFO DMA for different peripheral devices. DMA controllers support ring-buffer and double-buffer memory
data transactions.
To improve the bus efficiency, the DMA controllers provide an unaligned-word access function. When this function
is enabled, it can automatically convert the address format from the unaligned type to aligned type, ensuring
compliance with the AHB/APB protocol.