TrueTouch™ Multi-Touch Controller - CY8CTMA300E 技术规格

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"CYPRESS_CY8CTMA300E是赛普拉斯（Cypress Semiconductor Corporation）推出的TrueTouch™ Multi-Touch All-Points Touchscreen Controller，主要用于TMA3XX系列芯片的操作。这款控制器设计用于触摸屏设备，具有高性能和高耐受性的特点。" 赛普拉斯的CY8CTMA300E/301E是一款先进的电容式触摸屏控制器，主要特性包括： 1. **单芯片多触点技术**：该控制器能处理无限数量的独立触点，每个触点的位置都能被精确追踪。 2. **高密度感应点**：支持多达32个感应引脚，可以检测到256个交叉点，适应各种复杂的触摸输入。 3. **大屏幕支持**：可支持最大4.5英寸对角线的显示屏，满足各种尺寸的触摸设备需求。 4. **高精度**：无噪声时的典型分辨率可达0.1毫米，核心精度小于0.7毫米，确保了触摸位置的准确识别。 5. **快速扫描时间**：扫描时间为2.9毫秒，对应345Hz的扫描频率，提供了流畅的用户交互体验。 6. **双电源轨设计**：数字供电电压范围为1.71V至3.6V，模拟供电电压范围为2.7V至3.6V，提供了宽泛的工作电压选择。 7. **集成电压调节器**：无需额外的专用电压调节器，简化了系统设计。 8. **抗干扰能力强**：能够抵御屏幕上的水滴干扰，避免误触；即使手指湿润也能可靠追踪位置；对液晶显示（LCD）产生的噪声有免疫力；在嘈杂的射频（RF）环境中也能稳定运行。 9. **灵活的引脚配置**：每个感应引脚都可配置为接收器或发射器，增强了设计的灵活性。 10. **支持按钮和滑块功能**：除基本的触摸屏操作外，还支持触摸屏上的按钮和滑块控制，增加了用户界面的多样性。这些特性使得CY8CTMA300E成为适用于智能手机、平板电脑、工业设备等各类触摸屏应用的理想选择。开发人员可以利用这份文档来深入了解该控制器的功能和如何进行硬件及软件的集成，从而实现高效且可靠的触摸屏解决方案。

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CY8CTMA300E/301E

CONFIDENTIAL - RELEASED ONLY UNDER NONDISCLOSURE AGREEMENT (NDA)

Document Number: 001-55268 Rev. *I Page 5 of 26

Figure 2. Power Supply Connection

Note Lowest average power is achieved by sleeping after scanning and processing is complete. The scan time, T

SCAN

is the time it

takes to convert all intersection capacitances on the touchscreen to digital values. The process time, T

PROCESS

, is the time it takes

the CPU to process the digital values and resolve the finger position. The sleep time, T

SLEEP

, is the time, after the scanning and

processing, that the device is asleep. The refresh rate is the periodic time when fresh data is available to read from the device.

REFRESH

= T

SCAN

+ T

PROCESS

+ T

SLEEP

. For the fastest refresh time, T

SLEEP

= 0. In Table 1, three refresh rates were selected for

a 8 × 12 panel with a typical scan time of 2.9 ms and a process time of 1 ms for one finger touch. The 8- and 16-ms refresh rates are

typical rates for the host to track a finger position in real time. The 100-ms refresh rate saves power by waiting for a finger touch to

occur before changing to the faster 8- and 16-ms refresh rates. Average current and power numbers were calculated in the table by

using I

and I

CPIN

typical values from Table 7 on page 10 (F

IMO

= F

CPU

= 24 MHz) and the following equations.

Equation 1

Equation 2

Equation 3

1.8-V

LDO

Charge Pump

CPO

CPIN

CP+

CP–

CPO

CORE

Power

CY8CTMA30xE

2.2 µF

0.1 µF

2.7 V < V

= V

CPIN

< 3.6 V

1 µF

1.8-V

LDO*

Charge Pump

CPO

CPIN

CP+

CP–

CPO

CORE

Power

CY8CTMA30xE

2.2 µF

0.1 µF

1 µF

2.7 V V

CPIN

3.6 V

1.71 V V

CPIN

0.1 µF

Single Supply Connection Dual Supply Connection

* LDO is automatically bypassed when 1.8V is supplied

Table 1. Typical Average Currents and Power

Conditions T

REFRESH

[ms] I

DDAVG

[mA] I

CPINAVG

[mA]

Average Total Power

AVG

[mW]

= 1.8, V

CPIN

= 2.7 83.8 3.6 17

= 1.8, V

CPIN

= 2.7 16 1.9 1.8 8.3

= 1.8, V

CPIN

= 2.7 100 0.30 0.29 1.3

DDAVG

SCAN

PROCESS

+()×

REFRESH

--------------------------------------------------------------------=

CPINAVG

CPIN

SCAN

REFRESH

------------------------------------=

AVG

DDAVG

CPIN

CPINAVG

×+×=

[+] Feedback

CY8CTMA300E/301E

CONFIDENTIAL - RELEASED ONLY UNDER NONDISCLOSURE AGREEMENT (NDA)

Document Number: 001-55268 Rev. *I Page 6 of 26

Pin Information

The CY8CTMA300E/301E is available in several packages. This section provides the pin names, descriptions, and mapping to the

physical package.

Table 2. 36-Pin QFN (CY8CTMA300E/301E)

No.

Type

Name Description

CY8CTMA300E/301E

Digi-

tal

Analog

1 I/O I/O P0[1] GPIO / sense pin multiplexable to TX or RX sections of channel 0

2 I/O I/O P0[3] GPIO / sense pin multiplexable to TX or RX sections of channel 0

3 I/O I/O P3[0] GPIO / sense pin multiplexable to TX or RX sections of channel 1

4 I/O I/O P3[1] GPIO / sense pin multiplexable to TX or RX sections of channel 1

5 I/O I/O P3[2] GPIO / sense pin multiplexable to TX or RX sections of channel 1

6 I/O I/O P3[4] GPIO / sense pin multiplexable to TX or RX sections of channel 2

7 I/O I/O P3[5] GPIO / sense pin multiplexable to TX or RX sections of channel 2

8 I/O I/O P3[6] GPIO / sense pin multiplexable to TX or RX sections of channel 2

9 I/O I/O P0[4] GPIO / sense pin multiplexable to TX or RX sections of channel 3

10 I/O I/O P0[7] GPIO / sense pin multiplexable to TX or RX sections of channel 3

11 I/O I/O P2[7] GPIO / sense pin multiplexable to TX or RX sections of channel 3

12 I/O I/O P4[3] GPIO / sense pin multiplexable to TX or RX sections of channel 4

13 I/O I/O P4[2] GPIO / sense pin multiplexable to TX or RX sections of channel 4

14 I/O I/O P4[1] GPIO / sense pin multiplexable to TX or RX sections of channel 4

15 Power V

Connect to circuit ground

16 I/O I/O P1[0] GPIO / ISSP DATA / I

C SDA

17 I/O I/O P1[1] GPIO / ISSP CLK / I

C SCL

18 I/O I/O P1[4] ADC reference output. Bypass with 0.47 µF capacitor

19 Input XRES Active LOW external reset with internal pull-up

20 I/O I/O P4[6] GPIO / sense pin multiplexable to TX or RX sections of channel 5

21 I/O I/O P4[5] GPIO / sense pin multiplexable to TX or RX sections of channel 5

22 I/O I/O P4[4] GPIO / sense pin multiplexable to TX or RX sections of channel 5

23 I/O I/O P1[7] GPIO / I

C SCL

24 I/O I/O P1[5] GPIO / I

C SDA

25 I/O I/O P2[6] GPIO / sense pin multiplexable to TX or RX sections of channel 6

26 I/O I/O P0[0] GPIO / sense pin multiplexable to TX or RX sections of channel 6

27 I/O I/O P2[0] GPIO / sense pin multiplexable to TX or RX sections of channel 6

Power V

CPIN

Charge pump input. See Figure 2 on page 5 and Table 7 on page 10

29 Power V

CP–

Charge pump flying capacitor negative signal. See Figure 2 on page 5

Power V

CP+

Charge pump flying capacitor positive signal. See Figure 2 on page 5

31 Power V

CPO

Charge pump output. See Figure 2 on page 5 and Table 7 on page 10

Power V

Digital supply voltage. See Figure 2 on page 5 and Table 7 on page 10

33 I/O I/O P1[2] GPIO / sense pin multiplexable to TX or RX sections of channel 7

34 I/O I/O P2[1] GPIO / sense pin multiplexable to TX or RX sections of channel 7

35 I/O I/O P2[5] GPIO / sense pin multiplexable to TX or RX sections of channel 7

36 I/O I/O P2[3] GPIO / sense pin multiplexable to TX or RX sections of channel 0

EP – – – Exposed pad. Connect to circuit ground. See Figure 6 on page 16

QFN

(Top View)

P0[3]

P3[0]

P3[1]

P3[2]

P3[4]

P0[1]

P0[0]

P2[6]

P1[5]

P1[7]

P4[4]

[

]

[

]

[

]

[

]

[

]

36 35 34 33 32 31

[

]

[

]

[

]

P3[5]

[

]

P4[5]

P2[0]

[

]

P3[6]

P0[4]

[

]

[

]

P4[6]

XRES

–

[+] Feedback

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