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CONFIDENTIAL - RELEASED ONLY UNDER NONDISCLOSURE AGREEMENT (NDA)
Document Number: 001-55268 Rev. *I Page 6 of 26
Pin Information
The CY8CTMA300E/301E is available in several packages. This section provides the pin names, descriptions, and mapping to the
physical package.
Table 2. 36-Pin QFN (CY8CTMA300E/301E)
Pin
No.
Type
Name Description
CY8CTMA300E/301E
Digi-
tal
Analog
1 I/O I/O P0[1] GPIO / sense pin multiplexable to TX or RX sections of channel 0
2 I/O I/O P0[3] GPIO / sense pin multiplexable to TX or RX sections of channel 0
3 I/O I/O P3[0] GPIO / sense pin multiplexable to TX or RX sections of channel 1
4 I/O I/O P3[1] GPIO / sense pin multiplexable to TX or RX sections of channel 1
5 I/O I/O P3[2] GPIO / sense pin multiplexable to TX or RX sections of channel 1
6 I/O I/O P3[4] GPIO / sense pin multiplexable to TX or RX sections of channel 2
7 I/O I/O P3[5] GPIO / sense pin multiplexable to TX or RX sections of channel 2
8 I/O I/O P3[6] GPIO / sense pin multiplexable to TX or RX sections of channel 2
9 I/O I/O P0[4] GPIO / sense pin multiplexable to TX or RX sections of channel 3
10 I/O I/O P0[7] GPIO / sense pin multiplexable to TX or RX sections of channel 3
11 I/O I/O P2[7] GPIO / sense pin multiplexable to TX or RX sections of channel 3
12 I/O I/O P4[3] GPIO / sense pin multiplexable to TX or RX sections of channel 4
13 I/O I/O P4[2] GPIO / sense pin multiplexable to TX or RX sections of channel 4
14 I/O I/O P4[1] GPIO / sense pin multiplexable to TX or RX sections of channel 4
15 Power V
SS
Connect to circuit ground
16 I/O I/O P1[0] GPIO / ISSP DATA / I
2
C SDA
17 I/O I/O P1[1] GPIO / ISSP CLK / I
2
C SCL
18 I/O I/O P1[4] ADC reference output. Bypass with 0.47 µF capacitor
19 Input XRES Active LOW external reset with internal pull-up
20 I/O I/O P4[6] GPIO / sense pin multiplexable to TX or RX sections of channel 5
21 I/O I/O P4[5] GPIO / sense pin multiplexable to TX or RX sections of channel 5
22 I/O I/O P4[4] GPIO / sense pin multiplexable to TX or RX sections of channel 5
23 I/O I/O P1[7] GPIO / I
2
C SCL
24 I/O I/O P1[5] GPIO / I
2
C SDA
25 I/O I/O P2[6] GPIO / sense pin multiplexable to TX or RX sections of channel 6
26 I/O I/O P0[0] GPIO / sense pin multiplexable to TX or RX sections of channel 6
27 I/O I/O P2[0] GPIO / sense pin multiplexable to TX or RX sections of channel 6
28
Power V
CPIN
Charge pump input. See Figure 2 on page 5 and Table 7 on page 10
29 Power V
CP–
Charge pump flying capacitor negative signal. See Figure 2 on page 5
30
Power V
CP+
Charge pump flying capacitor positive signal. See Figure 2 on page 5
31 Power V
CPO
Charge pump output. See Figure 2 on page 5 and Table 7 on page 10
32
Power V
DD
Digital supply voltage. See Figure 2 on page 5 and Table 7 on page 10
33 I/O I/O P1[2] GPIO / sense pin multiplexable to TX or RX sections of channel 7
34 I/O I/O P2[1] GPIO / sense pin multiplexable to TX or RX sections of channel 7
35 I/O I/O P2[5] GPIO / sense pin multiplexable to TX or RX sections of channel 7
36 I/O I/O P2[3] GPIO / sense pin multiplexable to TX or RX sections of channel 0
EP – – – Exposed pad. Connect to circuit ground. See Figure 6 on page 16
QFN
(Top View)
1
2
3
4
5
6
P0[3]
P3[0]
P3[1]
P3[2]
P3[4]
P0[1]
27
26
25
24
23
22
P0[0]
P2[6]
P1[5]
P1[7]
P4[4]
1
5
1
4
1
3
1
2
1
1
1
0
P
4
[
1
]
P
4
[
2
]
P
4
[
3
]
P
2
[
7
]
P
0
[
7
]
36 35 34 33 32 31
P
2
[
5
]
P
2
[
1
]
P
1
[
2
]
V
D
D
V
C
P
O
7
P3[5]
V
S
S
1
6
P
1
[
0
]
21
P4[5]
30
V
C
P
+
P2[0]
P
2
[
3
]
8
P3[6]
9
P0[4]
1
7
P
1
[
1
]
1
8
P
1
[
4
]
20
P4[6]
19
XRES
29
V
C
P
–
28
V
C
P
I
N
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