![](https://csdnimg.cn/release/download_crawler_static/11928899/bg5.jpg)
512900002
2009-11-9
22
SEED-HPS6455
5
(010)51518855 FAX: (010)51518866
No.106 Zhichunlu,Haidian District,Beijing 100086
Telephone:
Address:
Title:
Sheet:
Rev:
Document No.:
Size:
D
A
1
2
3
4
5
6
Date:
OF
B
A
D
A
6
5
4
3
2
1
B
C
B
C
SEED Electronic Technology Ltd.
CLOSE TO DSP
CLOSE TO FPGA
FPGA SRIO
156.25M LVDS CLOCK
CLOSE TO DSP
CLOSE TO FPGA
cap close to output
M2
MGTTXP0_112
M3
MGTAVTTTX_112
N2
MGTTXN0_112
N1
MGTRXP0_112
N3
MGTAVTTRX_112
P1
MGTRXN0_112
T3
MGTAVCCPLL_112
R1
MGTRXN1_112
P3
MGTREFCLKN_112
T1
MGTRXP1_112
P4
MGTREFCLKP_112
T2
MGTTXN1_112
U3
MGTAVTTTX_112
U2
MGTTXP1_112
V5
MGTAVTTRXC
V4
MGTRREF_112
V2
MGTTXP0_114
AC3
MGTAVTTTX_114
W2
MGTTXN0_114
W1
MGTRXP0_114
W3
MGTAVTTRX_114
Y1
MGTRXN0_114
AB3
MGTAVCCPLL_114
AA1
MGTRXN1_114
Y3
MGTREFCLKN_114
AB1
MGTRXP1_114
Y4
MGTREFCLKP_114
AB2
MGTTXN1_114
V3
MGTAVTTTX_114
AC2
MGTTXP1_114
F2
MGTTXP0_116
F3
MGTAVTTTX_116
G2
MGTTXN0_116
G1
MGTRXP0_116
G3
MGTAVTTRX_116
H1
MGTRXN0_116
K3
MGTAVCCPLL_116
J1
MGTRXN1_116
H3
MGTREFCLKN_116
K1
MGTRXP1_116
H4
MGTREFCLKP_116
K2
MGTTXN1_116
L3
MGTAVTTTX_116
L2
MGTTXP1_116
U26-AV
XC5VSX50T
AD2
MGTTXP0_118
AD3
MGTAVTTTX_118
AE2
MGTTXN0_118
AE1
MGTRXP0_118
AE3
MGTAVTTRX_118
AF1
MGTRXN0_118
AH3
MGTAVCCPLL_118
AG1
MGTRXN1_118
AF3
MGTREFCLKN_118
AH1
MGTRXP1_118
AF4
MGTREFCLKP_118
AH2
MGTTXN1_118
AJ3
MGTAVTTTX_118
AJ2
MGTTXP1_118
B4
MGTTXP0_120
C4
MGTAVTTTX_120
B3
MGTTXN0_120
A3
MGTRXP0_120
C3
MGTAVTTRX_120
A2
MGTRXN0_120
D3
MGTAVCCPLL_120
C1
MGTRXN1_120
D4
MGTREFCLKN_120
D1
MGTRXP1_120
E4
MGTREFCLKP_120
D2
MGTTXN1_120
E3
MGTAVTTTX_120
E2
MGTTXP1_120
AK2
MGTTXP0_122
AK3
MGTAVTTTX_122
AL2
MGTTXN0_122
AL1
MGTRXP0_122
AL3
MGTAVTTRX_122
AM1
MGTRXN0_122
AM4
MGTAVCCPLL_122
AP2
MGTRXN1_122
AL4
MGTREFCLKN_122
AP3
MGTRXP1_122
AL5
MGTREFCLKP_122
AN3
MGTTXN1_122
AM3
MGTAVTTTX_122
AN4
MGTTXP1_122
U26-AW
XC5VSX50T
R3
MGTAVCC_112
R4
MGTAVCC_112
AA3
MGTAVCC_114
AA4
MGTAVCC_114
J3
MGTAVCC_116
J4
MGTAVCC_116
AG3
MGTAVCC_118
AG4
MGTAVCC_118
D5
MGTAVCC_120
F4
MGTAVCC_120
AJ4
MGTAVCC_122
AK5
MGTAVCC_122
U4
FLOAT
U26-AX
XC5VSX50T
U5
NC
B10
MGTTXP0_124
C10
MGTAVTTTX_124
B9
MGTTXN0_124
A9
MGTRXP0_124
C9
MGTAVTTRX_124
A8
MGTRXN0_124
C6
MGTAVCCPLL_124
A7
MGTRXN1_124
C8
MGTREFCLKN_124
A6
MGTRXP1_124
D8
MGTREFCLKP_124
B6
MGTTXN1_124
C5
MGTAVTTTX_124
B5
MGTTXP1_124
AN5
MGTTXP0_126
AM10
MGTAVTTTX_126
AN6
MGTTXN0_126
AP6
MGTRXP0_126
AM6
MGTAVTTRX_126
AP7
MGTRXN0_126
AM9
MGTAVCCPLL_126
AP8
MGTRXN1_126
AM7
MGTREFCLKN_126
AP9
MGTRXP1_126
AL7
MGTREFCLKP_126
AN9
MGTTXN1_126
AM5
MGTAVTTTX_126
AN10
MGTTXP1_126
C7
MGTAVCC_124
D7
MGTAVCC_124
AL8
MGTAVCC_126
AM8
MGTAVCC_126
U26-AY
XC5VSX50T
R191
49.9
1%
R192
NP/49.9
1%
C89
0.1uF
C96
0.1uF
C101
0.1uF
C100
0.1uF
C118
0.1uF
C115
0.1uF
C120
0.1uF
C122
0.1uF
C104
0.1uF
C106
0.1uF
C111
0.1uF
C108
0.1uF
C124
0.1uF
C123
0.1uF
C126
0.1uF
C128
0.1uF
L12
C73
0.1uF
L27
C263
0.1uF
L30
C270
0.1uF
L17
C82
0.1uF
L31
C292
0.1uF
L13
C74
0.1uF
L33
C307
0.1uF
L29
C269
0.1uF
L32
C302
0.1uF
L14
C75
0.1uF
L25
C246
0.1uF
L15
C69
0.1uF
L16
C76
0.1uF
1
INH
2
NC
5
OUT-
6
VDD
3
GND
4
OUT+
Y2
XTAL_6PIN_DIFF
C62
0.1uF
C141
0.01uF
C142
0.01uF
15
1Z
10
4Y
16
1Y
7
B
6
A
11
3Z
5
GND
12
3Y
4
VCC
8
EN4
3
EN3
13
2Z
2
EN2
14
2Y
1
EN1
9
4Z
U31
SN65LVDS104PW
C90
0.1uF
C347
0.01uF
C360
0.01uF
R209
100
1%
C127
0.01uF
C130
0.01uF
R186
100
1%
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
SRIO_CLK_FPGA
[5]
SRIO_CLK_FPGA
[5]
+AVTTRXC
[5]
FPGA_112_RX1
[5]
FPGA_112_RX1
[5]
FPGA_112_RX0
[5]
FPGA_112_RX0
[5]
FPGA_112_TX0
[5]
FPGA_112_TX0
[5]
FPGA_112_TX1
[5]
FPGA_112_TX1
[5]
+AVTTTX_112
[5]
+AVCC_PLL_112
[5]
+AVTTRX_112
[5]
+AVCC_112
[5]
FPGA_114_RX0
[5]
FPGA_114_RX0
[5]
FPGA_114_TX0
[5]
FPGA_114_TX0
[5]
FPGA_114_RX1
[5]
FPGA_114_RX1
[5]
FPGA_114_TX1
[5]
FPGA_114_TX1
[5]
+AVTTTX_114
[5]
+AVCC_PLL_114
[5]
+AVTTRX_114
[5]
+AVTTTX_116
[5]
+AVCC_PLL_116
[5]
+AVTTRX_116
[5]
+AVCC_114
[5]
+AVCC_116
[5]
FPGA_112_RX0
[5]
DSP_TX0
[19]
FPGA_112_RX0
[5]
DSP_TX0
[19]
FPGA_112_RX1
[5]
DSP_TX1
[19]
FPGA_112_RX1
[5]
DSP_TX1
[19]
FPGA_112_TX0
[5]
DSP_RX0
[19]
FPGA_112_TX0
[5]
DSP_RX0
[19]
FPGA_112_TX1
[5]
DSP_RX1
[19]
FPGA_112_TX1
[5]
DSP_RX1
[19]
FPGA_114_RX0
[5]
DSP_TX2
[19]
FPGA_114_RX0
[5]
DSP_TX2
[19]
FPGA_114_RX1
[5]
DSP_TX3
[19]
FPGA_114_RX1
[5]
DSP_TX3
[19]
FPGA_114_TX0
[5]
DSP_RX2
[19]
FPGA_114_TX0
[5]
DSP_RX2
[19]
FPGA_114_TX1
[5]
DSP_RX3
[19]
FPGA_114_TX1
[5]
DSP_RX3
[19]
+1.0V_FPGA_AVCC
+AVCC_112
[5]
+1.2V_FPGA
+AVCC_PLL_112
[5]
+1.2V_FPGA
+AVTTTX_112
[5]
+1.2V_FPGA
+AVTTRX_112
[5]
+1.2V_FPGA
+AVTTRXC
[5]
+1.0V_FPGA_AVCC
+AVCC_114
[5]
+1.2V_FPGA
+AVCC_PLL_114
[5]
+1.2V_FPGA
+AVTTTX_114
[5]
+1.2V_FPGA
+AVTTRX_114
[5]
+1.0V_FPGA_AVCC
+AVCC_116
[5]
+1.2V_FPGA
+AVCC_PLL_116
[5]
+1.2V_FPGA
+AVTTTX_116
[5]
+1.2V_FPGA
+AVTTRX_116
[5]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
NC
[2,3,5,6,10,11,13,14,16,17,18,19,20]
+3.3V
LVDS_CLK
[5]
LVDS_CLK
[5]
LVDS_CLK
[5]
LVDS_CLK
[5]
+3.3V
+3.3V
SRIO_CLK_DSP
[19]
SRIO_CLK_DSP
[19]
SRIO_CLK_FPGA
[5]
SRIO_CLK_FPGA
[5]
+1.8V