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3. Avalon Memory-Mapped Interfaces

3.1. Introduction to Avalon Memory-Mapped Interfaces

You can use Avalon Memory-Mapped (Avalon-MM) interfaces to implement read and

write interfaces for Host and Agent components. The following are examples of

components that typically include memory-mapped interfaces:

• Microprocessors

• Memories

• UARTs

• DMAs

• Timers

Avalon-MM interfaces range from simple to complex. For example, SRAM interfaces

that have fixed-cycle read and write transfers have simple Avalon-MM interfaces.

Pipelined interfaces capable of burst transfers are complex.

MNL-AVABUSREF | 2021.05.27

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Figure 6. Example Agent Component

The 16-bit general-purpose I/O peripheral shown in the following figure only responds to write requests. This

component includes only the Agent signals required for write transfers.

Avalon-MM

Interface

(Avalon-MM

Agent Interface)

Application-

Specific

Interface

writedata[15..0]

write

clk

pio_out[15..0]

CLK_EN

D Q

Avalon-MM Peripheral

Each signal in an Avalon-MM agent corresponds to exactly one Avalon-MM signal role.

An Avalon-MM interface can use only one instance of each signal role.

3.2. Avalon Memory Mapped Interface Signal Roles

Signal roles define the signal types that Avalon memory mapped host and agent ports

allow.

This specification does not require all signals to exist in an Avalon memory mapped

interface. There is no one signal that is always required. The minimum requirements

for an Avalon memory mapped interface are readdata for a read-only interface, or

writedata and write for a write-only interface.

The following table lists signal roles for the Avalon memory mapped interface:

Table 9. Avalon Memory Mapped Signal Roles

Some Avalon memory mapped signals can be active high or active low. When active low, the signal name ends

with _n.

Signal Role

Width Direction Required Description

Fundamental Signals

address

1 - 64 Host → Agent No

Hosts: By default, the address signal represents a byte

address. The value of the address must align to the data width.

To write to specific bytes within a data word, the host must use

the byteenable signal. Refer to the addressUnits interface

property for word addressing.

Agents: By default, the interconnect translates the byte address

into a word address in the agent’s address space. From the

perspective of the agent, each agent access is for a word of

data.

For example, address = 0 selects the first word of the agent.

address = 1 selects the second word of the agent. Refer to the

addressUnits interface property for byte addressing.

byteenable

byteenable_n

2, 4,

8, 16,

32,

64,

128

Host → Agent No Enables one or more specific byte lanes during transfers on

interfaces of width greater than 8 bits. Each bit in byteenable

corresponds to a byte in writedata and readdata. The host

bit <n> of byteenable indicates whether byte <n> is being

continued...

3. Avalon Memory-Mapped Interfaces

MNL-AVABUSREF | 2021.05.27

Avalon

Interface Specifications

Send Feedback

Signal Role Width Direction Required Description

written to. During writes, byteenables specify which bytes are

being written to. Other bytes should be ignored by the agent.

During reads, byteenables indicate which bytes the host is

reading. Agents that simply return readdata with no side

effects are free to ignore byteenables during reads. If an

interface does not have a byteenable signal, the transfer

proceeds as if all byteenables are asserted.

When more than one bit of the byteenable signal is asserted,

all asserted lanes are adjacent.

debugaccess

1 Host → Agent No When asserted, allows the Nios II processor to write on-chip

memories configured as ROMs.

read

read_n

1 Host → Agent No

Asserted to indicate a read transfer. If present, readdata is

required.

readdata

8, 16,

32,

64,

128,

256,

512,

1024

Agent → Host No

The readdata driven from the agent to the host in response to

a read transfer. Required for interfaces that support reads.

response

[1:0]

2 Agent → Host No

The response signal is an optional signal that carries the

response status.

Note: Because the signal is shared, an interface cannot issue or

accept a write response and a read response in the same

clock cycle.

•

00: OKAY—Successful response for a transaction.

•

01: RESERVED—Encoding is reserved.

•

10: SLVERR—Error from an endpoint agent. Indicates an

unsuccessful transaction.

•

11: DECODEERROR—Indicates attempted access to an

undefined location.

For read responses:

•

One response is sent with each readdata. A read burst

length of N results in N responses. Fewer responses are not

valid, even in the event of an error. The response signal value

may be different for each readdata in the burst.

• The interface must have read control signals. Pipeline support

is possible with the readdatavalid signal.

•

On read errors, the corresponding readdata is "don't care".

For write responses:

• One write response must be sent for each write command. A

write burst results in only one response, which must be sent

after the final write transfer in the burst is accepted.

•

If writeresponsevalid is present, all write commands

must be completed with write responses.

write

write_n

1 Host → Agent No

Asserted to indicate a write transfer. If present, writedata is

required.

writedata

8, 16,

32,

64,

128,

256,

512,

1024

Host → Agent No Data for write transfers. The width must be the same as the

width of readdata if both are present. Required for interfaces

that support writes.

Wait-State Signals

continued...

3. Avalon Memory-Mapped Interfaces

MNL-AVABUSREF | 2021.05.27

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Avalon

Interface Specifications

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