TI SN54BCT8374A：兼容IEEE 1149.1的扫描测试集成电路

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"TI-SN54BCT8374A.pdf 是一份技术文档，介绍了一款由德州仪器（Texas Instruments）生产的集成电路，属于SCOPE家族的测试性产品。该器件是SN54BCT8374A和SN74BCT8374A，功能上等同于'F374'和'BCT374'，但具有额外的测试功能，兼容IEEE 1149.1-1990标准的测试访问端口（Test Access Port, TAP）和边界扫描架构。" 正文: TI-SN54BCT8374A和SN74BCT8374A是八位D型边沿触发的触发器，设计用于集成电路的测试。这些器件在正常工作模式下与传统的'F374'和'BCT374'功能相同，但在测试模式下提供了增强的功能，这使得它们在生产和维护电子设备时具有更高的可测试性和诊断能力。该器件遵循IEEE 1149.1-1990标准，这是边界扫描测试方法的一个重要规范。边界扫描允许在不移动或重新连接测试引脚的情况下检查电路板上的组件，极大地提高了测试效率。通过TAP，测试操作可以同步进行，这使得在系统级进行故障隔离和调试变得更加便捷。 TI-SN54BCT8374A支持SCOPE指令集，这是德州仪器开发的一套测试指令，包括了IEEE 1149.1标准所需的指令，如INTEST、CLAMP和HIGHZ，以及一些可选功能。这些指令使得器件能够执行平行签名分析（输入的并行测试）、伪随机模式生成（通过输出端口）以及采样输入和切换输出等测试任务。此外，该器件还具有一种特殊功能，即通过识别TMSPin上的双高电平电压（10V）来实现可选的测试复位信号。这一特性使得在测试过程中能够更加灵活地控制设备的状态。封装选项多样，包括塑料小外形（DW）封装，陶瓷芯片载体（FK），以及标准的塑料（NT）和陶瓷（JT）300-mil DIP封装，以满足不同应用环境和设计需求。 TI-SN54BCT8374A和SN74BCT8374A是针对电子测试和诊断领域设计的高性能集成电路，其兼容性和灵活性使其成为电路板级测试解决方案的理想选择。通过其强大的测试功能和多种封装选项，这些器件能够适应广泛的工业、商业和航空航天应用。

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SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E − JUNE 1990 − REVISED JULY 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard

1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the

synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip

control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and

output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully

one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the

device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a

2-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

Run-Test/Idle Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = LTMS = H

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = LTMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = HTMS = H

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E − JUNE 1990 − REVISED JULY 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.

The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller

proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in

the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive

TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left

unconnected or if a board defect causes it to be open circuited.

For the ’BCT8374A, the instruction register is reset to the binary value 11111111, which selects the BYPASS

instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.

The test operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

When a data register scan is selected, the TAP controller must pass through the Capture-DR state. In the

Capture-DR state, the selected data register may capture a data value as specified by the current instruction.

Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the

Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the

first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic

level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

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