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PM0215 The STM32 Cortex-M0 processor

Doc ID 022979 Rev 1 15/91

Execution program status register

The EPSR contains the Thumb state bit.

See the register summary in Table 3 on page 12 for the EPSR attributes. The bit

assignments are:

Attempts to read the EPSR directly through application software using the MSR instruction

always return zero. Attempts to write the EPSR using the MSR instruction in application

software are ignored. Fault handlers can examine EPSR value in the stacked PSR to

indicate the operation that is at fault. See Section 2.3.6: Exception entry and return on

page 25.

The following can clear the T bit to 0:

● instructions BLX, BX and POP{PC}

● restoration from the stacked xPSR value on an exception return

● bit[0] of the vector value on an exception entry.

Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See

Lockup on page 28 for more information.

Interruptable-restartable instructions

LDM and STM are interruptable-restartable instructions. If an interrupt occurs during the

execution of one of these instructions, the processor abandons execution of the instruction.

After servicing the interrupt, the processor restarts execution of the instruction from the

beginning.

Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks or code sequences.

To disable or re-enable exceptions use the MSR and MRS instructions, or the CPS

instruction to change the value of PRIMASK. See MRS on page 64, MSR on page 65, and

CPSID CPSIE on page 62 for more information.

Priority mask register

The PRIMASK register prevents activation of all exceptions with configurable priority. See

the register summary in Table 3 on page 12 for its attributes.

Figure 4. PRIMASK register bit assignments

Table 7. EPSR bit definitions

Bits Description

Bits 31:25 Reserved.

Bit 24 T: Thumb state bit.

Bits 23:0 Reserved.

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PM0215 The STM32 Cortex-M0 processor

Doc ID 022979 Rev 1 17/91

2.1.4 Exceptions and interrupts

The Cortex-M0 processor supports interrupts and system exceptions. The processor and

the NVIC prioritize and handle all exceptions. An exception changes the normal flow of

software control. The processor uses handler mode to handle all exceptions except for

reset. See Exception entry on page 26 and Exception return on page 27 for more

information. The NVIC registers control interrupt handling. See Nested vectored interrupt

controller (NVIC) on page 70 for more information.

2.1.5 Data types

The processor manages all memory accesses as little-endian. See Memory regions, types

and attributes on page 19 for more information. It supports the following data types:

● 32-bit words

● 16-bit halfwords

● 8-bit bytes

2.1.6 The Cortex microcontroller software interface standard (CMSIS)

ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for

programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device

driver library. For a Cortex-M0 microcontroller system, the Cortex Microcontroller Software

Interface Standard (CMSIS) defines:

● A common way to:

– Access peripheral registers

– Define exception vectors

● The names of:

– The registers of the core peripherals

– The core exception vectors

● A device-independent interface for RTOS kernels.

The CMSIS includes address definitions and data structures for the core peripherals in the

Cortex-M0 processor.

The CMSIS simplifies software development by enabling the reuse of template code and the

combination of CMSIS-compliant software components from various middleware vendors.

Software vendors can expand the CMSIS to include their peripheral definitions and access

functions for those peripherals.

This document includes the register names defined by the CMSIS, and gives short

descriptions of the CMSIS functions that address the processor core and the core

peripherals.

Note: This document uses the register short names defined by the CMSIS. In a few cases these

differ from the architectural short names that might be used in other documents.

The following sections give more information about the CMSIS:

● Power management programming hints on page 30

● CMSIS intrinsic functions on page 35

● Interrupt set-enable register (ISER) on page 71

● NVIC programming hints on page 75

PM0215 The STM32 Cortex-M0 processor

Doc ID 022979 Rev 1 19/91

2.2.1 Memory regions, types and attributes

The memory map is split into regions. Each region has a defined memory type, and some

regions have additional memory attributes. The memory type and attributes determine the

behavior of accesses to the region.

The memory types are:

The different ordering requirements for Device and Strongly-ordered memory mean that the

memory system can buffer a write to Device memory, but must not buffer a write to Strongly-

ordered memory.

Additional memory attributes include:

2.2.2 Memory system ordering of memory accesses

For most memory accesses caused by explicit memory access instructions, the memory

system does not guarantee that the order in which the accesses complete matches the

program order of the instructions, providing this does not affect the behavior of the

instruction sequence. Normally, if correct program execution depends on two memory

accesses completing in program order, software must insert a memory barrier instruction

between the memory access instructions, see Section 2.2.4: Software ordering of memory

accesses on page 20.

However, the memory system does guarantee some ordering of accesses to Device and

Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs

before A2 in program order, the ordering of the memory accesses caused by two

instructions is:

Normal The processor can re-order transactions for efficiency, or

perform speculative reads.

Device The processor preserves transaction order relative to other

transactions to Device or Strongly-ordered memory.

Strongly-ordered The processor preserves transaction order relative to all other

transactions.

Execute Never (XN) Means the processor prevents instruction accesses. Any

attempt to fetch an instruction from an XN region causes a

HardFault exception.

Table 10. Ordering of memory accesses

(1)

1. - means that the memory system does not guarantee the ordering of the accesses.

< means that accesses are observed in program order, that is, A1 is always observed before A2.

A1

A2

Normal access

Device access Strongly

ordered

access

Non-shareable Shareable

Normal access - - - -

Device access, non-shareable - < - <

Device access, shareable - - < <

Strongly ordered access - < < <

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