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Preface
xviii
The continued demand for ever thinner electronic packages has led to
mechanical challenges. A simple method of thinning a package is to start with
a thinner die. However, the latest wafer technologies are strain‐engineered, so
any bending of thin devices (<80 μm) can impact device performance.
Furthermore, the handling of thin die can be difficult and costly, so it is often
preferable to avoid the use of thinned die. Packaging technologies like embed-
ded and FO‐WLP enable a low package height by eliminating the substrate
while still being able to use die thicker than 80 μm.
Modern electronic packages must also be highly reliable. The CTE mismatch
between the materials in a package, including the mold compound, substrate,
and interconnect, can induce mechanical stress. Minimizing this mismatch is
one key to good package reliability; however, the elimination of interconnects
and substrates can also eliminate these stresses. Warpage control is another
important consideration. Warpage can be managed through the properties of
the materials that make up the package, such as CTE, glass transition tempera-
ture (T
g
), and modulus. The adjustment of core, prepreg, and solder resist layer
thicknesses and copper density can also help manage warpage. However, elimi-
nation of the substrate altogether can eliminate the risk of warpage. Thus,
these and other mechanical challenges can be addressed with embedded and
FO‐WLP packaging.
During the electrical design of an electronic package, signal integrity, power
distribution, and any functional partitioning must be taken into account. The
package should not degrade the electrical performance of the device. Thus,
interconnect lengths must be short to minimize parasitics in the package, a low
resistance is required to support the on‐chip power network, voltage drops
(V=IR) must be small, multiple parallel power and ground pins are necessary,
and dummy metal planes are introduced for grounding. Since embedded and
FO‐WLP packaging can eliminate substrates and interconnects allowing for
shorter packaging routing circuitry from die to solder ball, these electrical con-
cerns are addressed.
In packaging, poor thermal paths, no airflow, closed systems, and 3D inte-
gration all exacerbate thermal issues. The thermal resistances of the epoxy
mold compound, device, interconnect, substrate, and the ball grid array (BGA)
for BGA and chip‐scale packages (CSP) must be taken into account. The
junction temperature or operating temperature of the device (T
j
) must be
minimized for a given power to prevent device failure. The thermal paths of
embedded and FO‐WLP packages are minimized by elimination of the
substrate.
In embedded and FO‐WLP packaging, a device is embedded into an organic
laminate substrate or mold compound, respectively. There are many types of
embedded and FO‐WLP packages offered in the market today, such as extended
wafer‐level ball grid array (eWLB), redistributed chip package (RCP), M‐Series,
integrated fan‐out (InFO), embedded chip package (ECP), and semiconductor