三维集成与射频SiP技术新进展：嵌入式与扇出晶圆级封装探索

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"《嵌入式和扇出晶圆级封装技术的进步》是一本深入探讨当前半导体封装领域前沿的专著，重点关注三维集成、异构集成以及系统级封装（System-in-Package, SiP）在射频设计中的应用。作者贝丝·凯瑟博士和斯蒂芬·克罗恩特编辑，该书于2019年首次出版。书中详细介绍了这些先进技术如何推动电子组件的微型化、高效性和性能提升，特别是在射频集成电路（RF IC）设计中的三维集成电路技术和微系统设计。三维集成是书中的核心主题，它通过在单一硅片上构建多层电路，实现了更高的密度和信号完整性。这种技术包括堆叠芯片（Stacked Chip）、三维立体封装（3D Stacked Packaging）和通过薄膜互连（Trench Isolation and Through-Silicon Vias, TSVs）实现的垂直连接。这些技术有助于减少功耗，提高散热效率，并为更复杂的功能集成创造可能。异构集成则关注不同材料和工艺的结合，如CMOS与非CMOS技术的融合，以增强系统性能和扩展功能。例如，在射频领域，这可能涉及碳纳米管、硅 carbide 或其他新型材料的应用，旨在开发高性能的滤波器、放大器和信号处理器。 SiP设计则是封装技术的重要分支，它将多个功能单元（如逻辑、存储、射频等）封装在一个单一的封装体内，简化了系统设计，提高了模块间的互操作性和可靠性。在射频SiP中，组件间的信号传输距离缩短，延迟减小，从而提升了整体系统的性能和带宽。书中还涵盖了微系统设计的相关内容，包括软硬件协同优化、电源管理策略以及散热策略，所有这些都是在现代电子产品日益小型化和高性能化背景下至关重要的。此外，版权信息表明，读者在使用书中的内容时必须遵守 Wiley 的版权政策，以确保合法合规。《嵌入式和扇出晶圆级封装技术的进步》为读者提供了对当今先进封装技术在射频和微系统设计中的最新进展和实践的全面理解，对于工程师、研究人员和行业专业人士来说，是一本极具价值的参考和学习资料。随着技术的不断进步，这本书将继续为电子封装领域的发展提供指导。"

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Contents

xiv

18 Tools forFan‐Out Wafer‐Level Package Processing 403

Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung

18.1 Turnkey Solution forFan‐Out Wafer‐Level Packaging 403

18.2 Die Placement Process andTools forFO‐WLP 404

18.3 Encapsulation Tool forLarge Format Encapsulation 408

18.4 The Test Handling andPacking Solution forWafer‐Level Packaging

andFO‐WLP 415

References 417

19 Equipment andProcess foreWLB: Required PVD/Sputter

Solutions

419

Chris Jones, Ricardo Gaio, and José Castro

19.1 Background 419

19.2 Process Flow 422

19.2.1 Degas 422

19.2.2 Pre‐clean 422

19.2.3 PVD Adhesion Layer Deposition 422

19.2.4 Cu Seed Layer Deposition 423

19.3 Equipment Challenges forFO‐WLP 423

19.3.1 Contamination 423

19.3.2 Increased I/O Density 425

19.3.3 Organic Passivation Particle Management 426

19.3.4 Contact Resistance (R

) Management 426

19.3.5 Wafer Warpage 427

19.3.6 Capital Cost 427

19.4 Equipment Developed toOvercome Challenges 428

19.4.1 Solution forContamination 428

19.4.2 Atmospheric Degas vs. Vacuum Degas 429

19.4.3 Solutions forIncreased I/O Density 430

19.4.4 Solution forParticle Management 431

19.4.5 Solution forR

Management 431

19.4.6 Why Soft ICP Etch Is Best 433

19.4.7 Solution forWafer Warpage 434

19.4.8 Solution forCapital Cost Reduction 435

19.5 Additional Equipment Features 436

19.6 Design Rules Related totheEquipment 437

19.7 Reliability 438

19.8 Next Steps 438

References 440

20 Excimer Laser Ablation forthe Patterning ofUltra‐fine Routings 441

Habib Hichri, Markus Arendt, and Seongkuk Lee

20.1 Advanced Packaging Applications andTechnology Trends 442

20.2 The High Density Structuring Challenge 443

xvii

Embedded and fan‐out wafer‐level packaging (FO‐WLP) are new electronic

packaging technologies that have entered the market over the last 10 years due

to a drive for low cost, high reliability, and large‐scale integration of semicon-

ductor devices for mobile, automotive, Internet of things (IoT), and medical

markets. These new packaging technologies also address other electronic

packaging challenges, including mechanical, materials, thermal, and electrical

performance.

When designing an electronic package, there are many material challenges

to consider, both in the semiconductor die and in the package. The die may

have fragile low dielectric and extreme low dielectric constant interlayer

dielectric (ILD) materials that must be taken into account. The stress on these

layers must be minimized to prevent cracking or delamination of the passiva-

tion. One solution to avoiding these potential failure modes is to eliminate the

interconnection between the device and substrate, reducing the stress on the

semiconductor die. The pitch of the interconnects on the die is another consid-

eration. For traditional packaging solutions such as wire bond and flip chip, the

pitch of the wire bonds or flip‐chip solder interconnects can be limited, such as

in wire‐bond packaging; the ability to wire bond or route the interconnection

in the substrate, for example, can limit the minimum pitch. In flip‐chip packag-

ing, the ability to chip attach at fine pitch, to underfill fine‐pitch interconnects,

and to route the substrate at fine pitches can be a limiter. Again, it is best to

eliminate the interconnections altogether to minimize the pitch. Flip‐chip

packaging also has the challenge of introducing low coefficient of thermal

expansion (CTE) and high modulus substrate materials. These materials are

required in order to minimize warpage in a package. Also, low CTE mold

materials must be used to mitigate the stress introduced due to the CTE

mismatch between the device, the substrate, and the interconnect material.

A solution that eliminates the substrate and the interconnect, such as embedded

and FO‐WLP, is preferred. These material challenges have led to the development

of substrate‐ and interconnect‐free embedded packages.

Preface

xviii

The continued demand for ever thinner electronic packages has led to

mechanical challenges. A simple method of thinning a package is to start with

a thinner die. However, the latest wafer technologies are strain‐engineered, so

any bending of thin devices (<80 μm) can impact device performance.

Furthermore, the handling of thin die can be difficult and costly, so it is often

preferable to avoid the use of thinned die. Packaging technologies like embed-

ded and FO‐WLP enable a low package height by eliminating the substrate

while still being able to use die thicker than 80 μm.

Modern electronic packages must also be highly reliable. The CTE mismatch

between the materials in a package, including the mold compound, substrate,

and interconnect, can induce mechanical stress. Minimizing this mismatch is

one key to good package reliability; however, the elimination of interconnects

and substrates can also eliminate these stresses. Warpage control is another

important consideration. Warpage can be managed through the properties of

the materials that make up the package, such as CTE, glass transition tempera-

ture (T

), and modulus. The adjustment of core, prepreg, and solder resist layer

thicknesses and copper density can also help manage warpage. However, elimi-

nation of the substrate altogether can eliminate the risk of warpage. Thus,

these and other mechanical challenges can be addressed with embedded and

FO‐WLP packaging.

During the electrical design of an electronic package, signal integrity, power

distribution, and any functional partitioning must be taken into account. The

package should not degrade the electrical performance of the device. Thus,

interconnect lengths must be short to minimize parasitics in the package, a low

resistance is required to support the on‐chip power network, voltage drops

(V=IR) must be small, multiple parallel power and ground pins are necessary,

and dummy metal planes are introduced for grounding. Since embedded and

FO‐WLP packaging can eliminate substrates and interconnects allowing for

shorter packaging routing circuitry from die to solder ball, these electrical con-

cerns are addressed.

In packaging, poor thermal paths, no airflow, closed systems, and 3D inte-

gration all exacerbate thermal issues. The thermal resistances of the epoxy

mold compound, device, interconnect, substrate, and the ball grid array (BGA)

for BGA and chip‐scale packages (CSP) must be taken into account. The

junction temperature or operating temperature of the device (T

) must be

minimized for a given power to prevent device failure. The thermal paths of

embedded and FO‐WLP packages are minimized by elimination of the

substrate.

In embedded and FO‐WLP packaging, a device is embedded into an organic

laminate substrate or mold compound, respectively. There are many types of

embedded and FO‐WLP packages offered in the market today, such as extended

wafer‐level ball grid array (eWLB), redistributed chip package (RCP), M‐Series,

integrated fan‐out (InFO), embedded chip package (ECP), and semiconductor

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