2018 Custom Integrated Circuits Conference 特别专题介绍

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"这篇文章摘自IEEE Journal of Solid-State Circuits 2019年3月刊，该期刊专注于固态电路领域的深入研究，特别是集成电路的晶体管级设计。本期刊的文章都经过同行评审，遵循IEEE PSPB Operations Manual的评审规定，采用单盲审稿制度。在2018年定制集成电路会议特辑中，涵盖了多篇关于低功耗、高精度ADC设计及高速接收器技术的研究论文。" 在集成电路（IC）设计领域，本文着重介绍了2018年定制集成电路会议的部分研究成果，这些成果对低功耗、高效率的数字信号处理技术有重大贡献。首先，文章提到了一款11-nW的CMOS温度至数字转换器，它利用亚阈值电流在低于热电压下的工作方式，实现了极低功耗的温度测量。这种设计对于物联网设备和远程传感器网络的能源效率提升具有重要意义。接下来，文章介绍了噪声整形的VCO（压控振荡器）为基础的非均匀采样ADC（模数转换器），通过相位域的电平穿越技术，优化了信号处理性能。此ADC设计提高了频率分辨率，降低了噪声影响。此外，还有一篇关于10位SAR ADC（逐次比较型ADC）的论文，它采用了单元长度电容器和被动FIR滤波器，实现了紧凑的电路布局，降低了功耗并提升了转换精度。紧接着，一篇1-GS/s，12位，单通道流水线ADC的报告引起了关注，其特色在于采用死区降级环放大器，显著改善了信号带宽和信噪比。最后两篇论文则聚焦于高速PAM-4（四电平脉冲幅度调制）接收器的设计。第一款52-Gb/s的ADC接收器结合了比较器辅助的2位/阶段SAR ADC和部分展开的DFE（决定反馈均衡器），在65-nm CMOS工艺下实现。另一款56-Gb/s PAM4接收器则采用了低开销的技术，优化了基于阈值和边缘的DFE FIR和IIR滤波器 tap 自适应，同样在65-nm CMOS工艺中实现。这些研究论文展示了集成电路设计的最新进展，特别是在高速通信和低功耗传感应用中的创新解决方案。这些技术的进步不仅推动了数据传输速率的提升，还降低了系统能耗，对于未来5G通信、物联网和高性能计算等领域的技术发展具有深远影响。

LIU et al.: 130-nm FERROELECTRIC NVSoC WITH DIRECT PERIPHERAL RESTORE ARCHITECTURE 887

Fig. 3. Conﬁguration of peripheral devices in (a) typical embedded system

and (b) transient computing system. (c) Wake-up time breakdown of a transient

computing system based on NVP [8].

re-conﬁguration time is partly due to the large conﬁguration

data size and the low frequency of serial interface between

NVP and peripheral. But even if we assume that the serial

interface operates at 8 MHz, the conﬁguration data are only

16 bytes long, and the system has four peripheral devices,

the re-conﬁguration time is 64 μs, which is still 20× longer

than the data restore time of NVP. In addition, during the entire

re-conﬁguration procedure, the NVP is occupied and cannot

perform other computation tasks.

To address these challenges, a nonvolatile system-on-

chip (NVSoC) is designed, which integrates an on-chip

power management subsystem to minimize the requirement of

off-chip components, thereby opening the possibility to make

IoT devices more compact. And for the ﬁrst time, a direct

peripheral restore architecture is proposed to accelerate the

peripheral re-conﬁguration process.

The remainder of this paper is organized as follows.

Section II provides an overview of the proposed NVSoC.

Section III describes the integrated power management sub-

system. Section IV describes the direct peripheral restore

architecture. Section V presents the chip implementation and

its performance. Finally, Section VI concludes this paper.

II. S

YSTEM OVERVIEW

Fig. 4 shows the block diagram of the proposed NVSoC,

consisting of an integrated power management subsystem,

an RC oscillator, an enhanced NVP, and a nonvolatile RF

transmitter (NVRF) controller. The power management sub-

system monitors the supply voltage and manages the power

status as well as the backup/restore decisions. The NVRF

controller manages the conﬁguration and data packets of a

wireless transceiver. It includes a nonvolatile register array to

store the conﬁguration and data packets. After power resump-

tion, the NVRF controller directly conﬁgures the transceiver

and sends data packets without the intervention of NVP. All

the ﬂip-ﬂops in the NVP and the NVRF controller are imple-

Fig. 4. NVSoC block diagram.

mented using NVFFs (gray blocks in Fig. 4), while the NVP

and the NVRF controller have two individual NVFF drivers

to control the backup and restore operations. This allows

the two blocks to be restored simultaneously when resuming

from a power failure and to be switched

ON/OFF indepen-

dently by the power management subsystem. This paper uses

the same micro-architecture and NVFF as in our previous

work [8] while adding two 32-kB in-house designed FeRAM

as data memory and instruction memory to improve the system

integration. The FeRAM and NVFF in this paper employ

ferroelectric capacitors as NVM elements. The binary 0/1 is

stored in the ferroelectric capacitor as low/high capacitance,

of which the state can be retained without power supply.

In addition, a 2-kB instruction cache is adopted to allow the

NVP to turn FeRAM off so as to save active power and operate

at a higher clock frequency.

The major contributions of this paper are to: 1) design

an integrated power management subsystem with increased

ﬂexibility for transient computing systems; 2) propose a

direct peripheral restore architecture, which provides a scalable

solution to the peripheral re-conﬁguration overhead challenge;

and 3) fabricate an NVSoC in 130-nm ferroelectric-CMOS

process, which demonstrates the highest level of integration

and fastest startup speed among all the reported NVPs.

III. I

NTEGRATED POWER MANAGEMENT SUBSYSTEM

A. Overview and Operation Flow

Fig. 5(a) presents the power management subsystem

architecture, consisting of a reconﬁgurable supply detector,

apower-

ON reset generator, a load switch, a voltage regulator,

and a power status controller. The reconﬁgurable supply

detector monitors the voltage V

SUP

at the terminal of the

decoupling capacitor and switches DET if V

SUP

exceeds the

detection threshold V

T+

(or falls below V

T−

). The power-ON

reset generator senses the DET signal and generates the power

gating signal PG

for the load switch and the RST signal

for the power status controller. The voltage regulator provides

a 1.3-V internal supply to digital logic. The power status

controller manages the supply voltages V

DDx

(x = 1, 2, 3) and

backup/restore control signals BR

(x = 1, 2). The NVSoC is

divided into ﬁve power domains: PD

includes the voltage

regulator and the power status controller, PD

–PD

refer to

NVP, NVRF controller, and RC oscillator, respectively, and

888 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019

Fig. 5. (a) Power management subsystem architecture. (b) Operation ﬂow

for an entire

ON–OFF cycle.

refers to the always-on circuits, including the supply

detector and the power-

ON reset generator.

Fig. 5(b) presents the functional waveform of the power

management subsystem for an entire

ON–OFF cycle. At time t

SUP

is too low, and the NVSoC is in the OFF state to accu-

mulate energy. As V

SUP

exceeds V

T+

at time t

, the supply

detector outputs DET = 1andV

DD0

is turned on. After

DD0

settles, the power-ON reset generator sets RST = 1,

which resets the power status controller so that PD

–PD

are turned on. At time t

, the power status controller sets

= 1 (x = 1, 2) to control the NVFF drivers to perform a

restore operation. The NVSoC resumes its task after the restore

process ﬁnishes at time t

. Hereafter, it can turn off PD

–PD

depending on the application requirements. For example,

at time t

, the NVRF controller (PD

) is to be switched OFF.

To do this, the power status controller ﬁrst clears BR

initiate a backup operation and then turns off V

DD2

after the

backup operation ﬁnishes (at time t

). At time t

and t

and V

DD2

are set to 1 in the reverse order to switch

the NVRF controller

ON again. Finally, at time t

, V

SUP

falls

below V

T−

, leading to DET = RST = BR

= 0 (x = 2, 3).

The NVP and NVRF then back up data, and at time t

DDx

(x = 0, 1, 2, 3) goes low, and the NVSoC enters the

OFF state.

B. Reconﬁgurable Supply Detector

Fig. 6 presents the reconﬁgurable supply detector, consist-

ing of a pair of resistor voltage dividers (RVDs), a mode

multiplexer, a bandgap reference, a hysteresis voltage com-

parator, and an undervoltage-lockout (UVLO) circuit. It can

be conﬁgured as ﬁxed threshold mode or MPPT mode to

adapt to application scenarios with different input power

characteristics.

With CFG = 0, the supply detector works in the ﬁxed

threshold mode. The input voltage V

SUP

is divided by the

Fig. 6. Reconﬁgurable supply detector architecture and its conﬁguration.

RVD composed of R

–R

and compared with V

provided

by the bandgap. The feedback transistor M

enables hystere-

sis characteristic. The UVLO circuit ensures DET = 0incase

that V

SUP

is too low and the bandgap cannot provide V

This avoids undesired restore operations, which could possibly

cause data corruption. The detection thresholds V

FIX

T+

, V

FIX

T−

and

hysteresis window V

FIX

are given as

FIX

T +

= V



1 +



(1)

FIX

T −

= V



1 +

+ R



(2)

and V

FIX

= V

+ R

. (3)

Here, R

is a programmable resistor. By conﬁguring

SRA

[2:0]

, the detection window V can be set to 125–300 mV.

With CFG = 1, the supply detector operates in the

MPPT mode. This mode keeps the detection thresholds

TH+

and V

TH-

(hence the range of operating voltage) near

the MPP to achieve better utilization of ambient energy. The

fractional open-circuit voltage (FOCV) algorithm is used here,

which is based on the fact that the voltage corresponding to

MPP, V

MPP

, bears an approximately linear relationship to the

OCV V

of the energy harvester, i.e., V

MPP

= k · V

.For

example, the constant k is commonly between 0.7 and 0.8 for

photovoltaic (PV) arrays. The OCV is obtained from a pilot

energy harvester, divided by the RVD composed of R

−−R

and compared with a fraction of V

SUP

. Similar to the ﬁxed

threshold mode, the detection thresholds in the MPPT mode

MPPT

T+

, V

MPPT

T−

and hysteresis window V

MPPT

are given as

MPPT

T +

= V

+ R



1 +



(4)

MPPT

T −

= V

+ R



1 +

+ R



(5)

and V = V

+ R

. (6)

The factor k is determined by the resistance of R

and can be

set to 63%–90% by conﬁguring SRA

[5:3]

LIU et al.: 130-nm FERROELECTRIC NVSoC WITH DIRECT PERIPHERAL RESTORE ARCHITECTURE 889

Fig. 7. Schematic of the power-ON reset generator.

Fig. 8. (a) Architecture of the power status controller. (b) Power domain

conﬁgurations.

C. Power-ON Reset Generator

Fig. 7 shows the schematic of the power-

ON reset generator,

including a delay capacitor C

DLY

, a level shifter, and CMOS

logic gates. The delay capacitor introduces a time delay

between PG

and RST. During wake-up time, this delay

guarantees that V

DD0

settles before RST is applied to the

power status controller. And when a power outage is coming,

this delay keeps PG

= 0 until the backup operation is

completed. Here, the load switch M

ensures that only the

supply detector and the power-

ON reset generator are in

the always-on power domain (PD

). This design minimizes

the power consumption when the NVSoC is in

OFF state,

thus allowing more energy to be accumulated for the next

power-

ON cycle.

D. Power Status Controller

Fig. 8(a) shows the architecture of the power status con-

troller, including a control ﬁnite state machine (FSM), a

24-bit low-power timer, a clock multiplexer, and power mode

registers. An external low-frequency oscillator serves as a

clock source if the RC oscillator (PD

) is power gated. The

role of the power status controller is twofold. First, during

the power-up sequence, it senses the RST signal and turns on

–PD

in parallel. This allows the NVP and NVRF con-

troller to perform restore operation simultaneously. Second,

it allows the NVP to take control of the power status according

to the application requirements. For this purpose, the NVP

sends a power management command to modify the power

mode registers. Consequently, the power status controller turns

off the corresponding power domain (after a backup operation

if necessary). And the power-gated domain can be turned

on again either by a new command or by a preset timeout.

The low-power timer allows the NVP to set the timeout and

turn itself off. And after the timeout, the FSM can turn the

NVP on again. Otherwise, the NVP can be turned on again

only by external resets or power condition changes. Fig. 8(b)

shows the ﬁve power modes of the NVSoC (ACTIVE, NVP,

NVRF, TIMER, and

OFF) and the power consumption of these

modes. They provide system designers with ﬂexible power

management capabilities.

E. Use Cases of Power Management Subsystem

The proposed power management subsystem supports two

supply detector modes and ﬁve power modes. The supply

detector modes make the NVSoC applicable to different power

scenarios. For example, in converterless and storageless energy

harvesting systems, the NVSoC is directly powered by the

energy harvester. In this case, the MPPT mode helps the

NVSoC to achieve higher energy efﬁciency. And in battery-

powered systems or energy harvesting systems with large

storage, the power supply is stable. Then, the supply detector

operates in a ﬁxed threshold mode to avoid unnecessary

backup/restore operations. The multiple power modes in the

proposed NVSoC enable ﬁne-grained power management to

save active power in applications, such as wireless sensor node.

For example, in a simple sense-compute-transmit application,

the processor ﬁrst performs sensor read and computation, then

initializes the wireless module, and ﬁnally sends the data

packet. The conventional NVP has to be powered

ON during

the entire sense-compute-transmit procedure because all these

tasks are controlled by software. In contrast, the proposed

NVSoC can ﬁrst enter the ACTIVE mode to perform sensing

and computation, and at the same time, the conﬁguration of

the wireless module can be managed by the NVRF controller.

If the sensing and computing are faster than the wireless

module conﬁguration, the NVSoC can turn off the NVP and

enter NVRF mode. In this mode, the NVRF controller is

able to independently ﬁnish the conﬁguration and transmission

tasks. And if the computation is complex, the NVSoC can

also turn off the NVRF controller and enter the NVP mode to

save power. The TIMER mode allows the NVSoC to perform

periodical tasks without an additional off-chip controller.

IV. D

IRECT PERIPHERAL RESTORE ARCHITECTURE

A. Architecture Design

To explain the intuition behinds the direct peripheral restore

architecture, we ﬁrst take a close look at the conventional

method to restore the conﬁguration of the peripheral devices.

As discussed in Section I, this procedure is traditionally

implemented by software. The NVP ﬁrst fetches the peripheral

conﬁguration data from NVM and then conﬁgures the digital

interface [e.g., I2C and serial peripheral interface (SPI)].

Next, it sends instructions (including commands and register

values) to the peripheral device [19]. As shown in Fig. 9(a),

890 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 3, MARCH 2019

Fig. 9. Comparison of peripheral restore approaches. (a) Software

approach. (b) Direct peripheral restore architecture.

this approach comes with three major disadvantages. First,

the software-controlled data transmission from NVM to

the digital interface introduces time and energy overheads.

Second, the NVP is occupied during the entire peripheral

re-conﬁguration process, and hence, other tasks cannot be

executed. Finally, if the system contains multiple peripheral

devices, they have to be conﬁgured one-by-one due to the

sequential nature of software implementation, which further

slows down the system wake-up speed.

Fig. 9(b) shows the proposed direct peripheral restore archi-

tecture. The conﬁguration data are stored in an NVM-based

conﬁguration table. After power resumption, the peripheral

restore driver directly fetches data from the conﬁguration table

and sends commands and conﬁguration data into the peripheral

devices. This architecture yields three beneﬁts. First, the direct

NVM access shortens the data transmission distance and

thereby has less time and energy consumption than the soft-

ware approach. Second, the peripheral restore operations are

transparent to the NVP so that it can resume computing tasks

immediately after the resumption of power supply. Finally,

the peripheral devices are conﬁgured in parallel rather than in

sequence, which shortens the startup time when the system

has multiple peripheral devices.

The direct peripheral restore architecture is a universal

architectural solution to the peripheral conﬁguration problem.

Following this concept, we implemented an NVRF controller

in the NVSoC to directly restore an off-chip wireless trans-

ceiver after power resumption. In Section IV-B, the details of

the NVRF controller will be described.

B. NVRF Controller

Fig. 10 shows the block diagram of the NVRF controller,

including a nonvolatile register array, a control FSM, an SPI

Fig. 10. Block diagram of the NVRF controller and the NVRF_CFG register.

Fig. 11. Die photograph and summary of the NVSoC.

digital interface, an NVRF_CFG register, and an NVFF

driver. The nonvolatile register array stores the conﬁguration

information as well as the data packets of the transmitter in

two separate zones. The NVRF controller has two operation

modes. First, during the power-up sequence, it autonomously

initiates the re-conﬁguration process of the transmitter (this is

skipped if the restored value of the EN bit of the NVRF_CFG

or data transmission sequence by setting the START bit and

C/D bit (0 for conﬁguration and 1 for data transmission) of

the NVRF_CFG register. Bits 0–2 of the NVRF_CFG register

are volatile because these bits need to be cleared after a power

interruption.

The major challenge in implementing the NVRF controller

is the increased power and area. In this paper, the former is

remedied by ﬁne-grained power management. As discussed in

Section III-E, the NVRF controller is turned on only during

the conﬁguration and transmission procedures. And the area

penalty turns out to be trivial according to the measurement

results, which will be shown in Fig. 16.

V. I

MPLEMENTATION AND RESULTS

A. Chip Summary

Fig. 11 shows the die photograph and summary of the

NVSoC. It is fabricated using a 130-nm ferroelectric-CMOS

LIU et al.: 130-nm FERROELECTRIC NVSoC WITH DIRECT PERIPHERAL RESTORE ARCHITECTURE 891

TABLE II

OMPARISON OF REPORTED NVPs

process with a 1.3-V supply voltage for digital logic and a

3.3-V supply voltage for FeRAM, I/O, and analog circuits.

The total die area is 22.09 mm

. The NVSoC has 1910 dis-

tributed NVFFs. Two 32-kB FeRAM macros are used as

data memory and instruction memory, respectively. With the

data and instruction FeRAMs turned on, the maximum clock

frequency is 16 MHz, and the active power consumption is

371 μW/MHz. And with the FeRAMs turned off, the clock

frequency is up to 30 MHz, and the NVSoC consumes

234 μW/MHz. In this case, the NVSoC operates from an

instruction cache.

Table II compares the NVSoC with a few silicon veriﬁed

NVPs [4]–[11]. The NVSoC has the following advantages.

First, the power management subsystem is integrated on-chip,

which minimizes the number of external components and

hence the form-factor and mass of NVSoC-based IoT devices.

In addition, the reconﬁgurablility of the supply detection cir-

cuit makes the NVSoC applicable to versatile power sources.

Second, most of the previous NVPs [4]–[6], [8], [10] operate

in two power modes (ACTIVE and

OFF). The NVPs reported

in [9] and [11] add a RETENTION mode to sustain short

power interruptions and reduce the number of backup and

restore operations. In this paper, the NVSoC has ﬁve-level

power modes, which support both periodical and energy-driven

applications and provide more ﬂexibility in power manage-

ment strategies. Third, all previous NVPs have to conﬁgure the

peripheral devices by software. Instead, this paper features

the direct peripheral restore architecture. It enables parallel

re-conﬁguration of peripheral devices and allows the NVP to

resume its computation task immediately after power resump-

tion. Finally, the NVSoC integrates an instruction cache to

remedy the high power dissipation and limited clock frequency

constrained by the FeRAM. The beneﬁts of the instruction

cache will be discussed in Section V-C.

Table II also compares the active power, startup time,

throughput, and energy efﬁciency of the NVSoC with pre-

vious NVPs. For a fair comparison, we assume that all of

the NVPs and the NVSoC operate at 8 MHz (which is the

maximum clock frequency of NVP [4]) and perform a typi-

cal sense-compute-transmit task. In this application scenario,

the peripheral devices have 32-byte conﬁguration data in total,

and 4 bytes of data are sensed, averaged, and transmitted.

The throughput and the energy efﬁciency are deﬁned as how

many sense-compute-transmit tasks are ﬁnished within the

same time and with the same amount of energy, respectively.

The power supply is a 100-Hz square wave to emulate the

power failure in energy harvesting systems. The performances

of the previous NVPs [4]–[11] are estimated based on their

micro-architecture and on-chip bus protocol. There are two

reasons that the proposed NVSoC has higher active power than

the previous NVPs [4], [5], [8], which have similar CMOS

technology and NVM. First, the NVRF controller increases the

active power, but it can be turned off after the conﬁguration

and transmission procedure. Second, the level of integration

of the proposed NVSoC is higher, and the clock and power

management subsystems also increase the active power. Nev-

ertheless, the NVSoC still outperforms previous NVPs in

startup speed, efﬁciency, and throughput. This is because the

NVRF controller has lower time and energy overheads than

the software approach when sending conﬁguration and data

packets to the peripheral devices. In addition, the ﬁne-grained

power management saves average power and thereby increases

the energy efﬁciency.

B. Measurement Results

Fig. 12(a) shows the operating waveform of the NVSoC

for an

OFF–ON cycle. A square-wave signal with 0–3.3-V

amplitude, 100-Hz frequency, and 90% duty cycle is applied

as a power source to emulate the power failures in an energy

harvesting scenario. To verify successful data backup and

restore operations, the NVSoC runs a counter program, and

the counter value is measured through GPIO.Awireless

transceiver ML7266 is connected to the NVSoC via SPI

interface, of which the waveform is captured to measure the

re-conﬁguration time after power resumption. As Fig. 12(a)

shows, the counter value changes from 0 × 46 to 0 × 00

during the power failure period because the supply voltage

drops to zero. And after the power is resumed, the counter

value is restored to 0 × 46. The waveforms of MOSI and

SCLK show that the system-level wake-up procedure (includ-

ing the re-conﬁguration of the transmitter) takes 1.23 ms.

Fig. 12(b) and (c) shows the backup and restore operations.

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2018 Custom Integrated Circuits Conference 特别专题介绍

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